Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2007-03-23
2008-12-16
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S226000
Reexamination Certificate
active
07466610
ABSTRACT:
A non-volatile semiconductor memory device comprises a redundant memory cell to store address data of a defect cell in a memory cell array. A first decoder circuit is given a first drive voltage to provide a control signal to the redundant memory cell. A dummy memory cell has a threshold voltage corresponding to the redundant memory cell. A second decoder circuit is given a second drive voltage corresponding to the first drive voltage to provide a control signal to the dummy memory cell. A comparator circuit compares data to be read out of the dummy memory cell with data actually read out of the dummy memory cell.
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patent: 6856543 (2005-02-01), Atsumi et al.
patent: 2006/0233014 (2006-10-01), Oh
patent: 2007/0038805 (2007-02-01), Eliason et al.
patent: 10-302476 (1998-11-01), None
Kashiwagi Jin
Umezawa Akira
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tran Michael T
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