Non-volatile semiconductor memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S314000, C257S315000, C257SE21209

Reexamination Certificate

active

07453118

ABSTRACT:
To propose a new channel structure suitable for high efficiency source side injection, and provide a non-volatile semiconductor memory device and a charge injection method using the same. The non-volatile memory device includes a first conductivity type semiconductor substrate (SUB), a first conductivity type inversion layer-forming region (CH1), second conductivity type accumulation layer-forming regions (ACLa, ACL2b), second conductivity type regions (S/D1, S/D2), an insulating film (GD0) and a first conductive layer (CL) formed on the inversion layer-forming region (CH1). A charge accumulation film (GD) and a second conductive layer (WL) are stacked on an upper surface and side surface of the first conductive layer (CL), an exposure surface of the inversion layer-forming region (CH1), and an upper surface of the accumulation layer-forming regions (ACLa, ACLb) and the second conductivity type regions (S/D1, S/D2). The second conductive layer (WL) is connected to a word line and second conductivity type regions (S/D1, S/D2) are connected to bit lines (Bla, BLb).

REFERENCES:
patent: 5604367 (1997-02-01), Yang
patent: 5729035 (1998-03-01), Anma
patent: 5838041 (1998-11-01), Sakagami et al.
patent: 5898619 (1999-04-01), Chang et al.
patent: 5925908 (1999-07-01), Dahl et al.
patent: 5930629 (1999-07-01), Fukumoto
patent: 5949706 (1999-09-01), Chang et al.
patent: 5969383 (1999-10-01), Chang
patent: 6157058 (2000-12-01), Ogura
patent: 6184093 (2001-02-01), Sung
patent: 6335554 (2002-01-01), Yoshikawa
patent: 6531350 (2003-03-01), Satoh et al.
patent: 6721205 (2004-04-01), Kobayashi et al.
patent: 6828624 (2004-12-01), Goda et al.
patent: 11-74389 (1999-03-01), None
Y. Hayashi, et al.,Twin MONOS Cell with Dual Control Gates, 2000 Symposium on VLSI Technology Digest of TEchnical Papers, 2000, pp. 122-123.
K-T Chang, et al.,A New SONOS Memory Using Source-Side Injection for Programming, IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 253-255.
Y. Ma, et al.,A Dual-bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single-Vcc High Density Flash Memories, International Electron Devices Meeting, 1994, pp. 57-60.
K. Naruke, et al.,A New Flash-Erase EEPROM Cell With a Sidewall Select-Gate on Its Source Side, International Electron Devices Meeting 1989, pp. 603-606.
M.H. White, et al.,On the Go with SONOS, IEEE Circuits & Devices, Jul. 2000, pp. 22-31.
S. Ogura, et al.,Low Voltage, Low Current, High Speed Program Step Split Gate with Ballistic Direct Injection for EEPROM/Flash, International Electron Devices Meeting 1998, pp. 987-990.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Non-volatile semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-volatile semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile semiconductor memory device will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4039766

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.