Non-volatile semiconductor memory device

Static information storage and retrieval – Systems using particular element – Resistive

Reexamination Certificate

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C365S158000

Reexamination Certificate

active

07002837

ABSTRACT:
The present invention is intended to realize executing high-speed program and erasure by using a NAND type memory cell unit that suits high degree of integration and to realize providing a highly reliable non-volatile semiconductor memory device. A memory cell is made up of a cell transistor (Tij) that is formed on the semiconductor substrate and a variable resistive element (Rij) that is connected between a source and drain terminals of the cell transistor (Tij) and the resistance value of that varies depending on applying a voltage and that is formed of the oxide having a perovskite structure that contains manganese. By connecting a plurality of the memory cells in series, there is formed a memory cell connected-in-series part. Then a memory cell block is prepared by providing a selection transistor (Si) to at least one end of the memory cell connected-in-series part. By disposing more than one such memory cell block, there is constructed a memory cell array.

REFERENCES:
patent: 5119329 (1992-06-01), Evans et al.
patent: 5894447 (1999-04-01), Takashima
patent: 6226197 (2001-05-01), Nishimura
patent: 6331943 (2001-12-01), Naji et al.
patent: 2003/0001178 (2003-01-01), Hsu et al.
patent: 2003/0003674 (2003-01-01), Hsu et al.
patent: 1 162 672 (2001-12-01), None
European Search Report mailed Jul. 1, 2004, for EP Application No. 04251240.0, three pages.

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