Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-18
2004-06-01
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S320000, C257S324000
Reexamination Certificate
active
06744106
ABSTRACT:
Japanese Patent Application No. 2001-221787 filed on Jul. 23, 2001, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device including memory cells, each having two non-volatile memory elements controlled by one word gate and two control gates.
As one type of non-volatile semiconductor memory device, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or Substrate) device is known. In the MONOS non-volatile semiconductor memory device, a gate insulating layer between a channel and a gate is formed of a laminate consisting of a silicon oxide film, silicon nitride film, and silicon oxide film. Charges are trapped in the silicon nitride film.
The MONOS non-volatile semiconductor memory device is disclosed in the literature (Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123). This literature discloses a MONOS flash memory cell including two non-volatile memory elements (MONOS memory cells) controlled by one word gate and two control gates. Specifically, one flash memory cell has two charge trap sites. A memory cell array region is formed by arranging a plurality of MONOS flash memory cells having such a structure in the row direction and the column direction.
In order to drive the MONOS flash memory cell, two bit lines, one word line, and two control gate lines are necessary. However, in the case of setting different control gates at the same potential when driving a large number of memory cells, these lines may be connected in common.
The operations of the flash memory consist of erasing, programming, and reading of data. Programming and reading of data are generally performed in 8-bits or 16-bits of selected cells at the same time. Erasing of data can be performed at the same time over a wider region.
A problem relating to this type of non-volatile memory is disturbance of data. The disturbance of data refers to the following phenomenon. When a high potential is applied to the control gate lines and the bit lines in the selected cells for programming or erasing, the high potential is also applied to the cells in a non-selected sector region through shared interconnects. As a result, the data in the non-selected cells is programmed or erased each time programming or erasing is performed, whereby the data in the non-selected cells is disturbed.
Such a phenomenon can be prevented by providing select gate circuits so that the high potential is applied only to the control gates in the cells in the selected sector, but is not applied to the control gates in the cells in the non-selected sector.
However, since this causes a voltage drop to occur in the select gate, a voltage for the voltage drop must be added in order to supply the high potential to the control gates in the cells in the selected sector at the time of programming or erasing. This hinders low voltage driving, whereby such a non-volatile memory cannot be applied to equipment for which a decrease in power consumption is needed, such as portable equipment.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention may provide a non-volatile semiconductor memory device enabling high-speed access when reading/writing while preventing the disturbance of data in the cells in the non-selected sector when programming or erasing in the selected cells.
The present invention may also provide a non-volatile semiconductor memory device capable of increasing the degree of integration of the memory cells while enabling high-speed access at the time of reading/writing.
Furthermore, the present invention may provide a non-volatile semiconductor memory device capable of reducing power consumption.
One aspect of the present invention provides a non-volatile semiconductor memory device comprising a memory cell array region in which are disposed a plurality of memory cells in first and second directions intersecting each other, each of the memory cells having first and second non-volatile memory elements that are controlled by one word gate and first and second control gates, and a control gate drive section which drives the first and second control gates of the memory cells within the memory cell array region.
The memory cell array region is divided in the second direction into a plurality of sector regions.
The control gate drive section has a plurality of control gate drivers each of which corresponds to one of the sector regions.
Each of the sector regions is divided in the first direction into a plurality of block regions, and each of the block regions has a plurality of memory cells. Each of the block regions has a plurality of sub bit lines respectively connected to the memory cells and extending in the first direction. A plurality of main bit lines are provided over the plurality of block regions extending in the first direction, and each of the main bit lines is commonly connected to the sub bit lines within the block regions. A plurality of switching elements which select connection/disconnection are provided at connections between the main bit lines and the sub bit lines. Therefore, a selected sub bit line and a main bit line connected thereto can be put in a conducting state, and a non-selected sub bit line and a main bit line connected thereto can be put in a non-conducting state, by the switching elements. As a result, since the interconnect capacitance of the bit lines can be decreased at the time of reading/writing, the memory cells can be accessed at a higher speed at the time of reading/writing.
The first control gate and the second control gate, which are connected with two memory cells adjacent in the second direction, are formed on either side of each of the sub bit lines. The first and second control gates formed on either side of each of the sub bit lines have two continuous portions in which end portions of the first and second control gates are connected. This enables the resistance of the control gates to be approximately halved in comparison with the case where the continuous portion is formed at end portions of the first and second control gates on only one side.
Each of the sub bit lines has a projecting portion in which one of the end portions project in the first direction outside end portion of an adjacent sub bit line among the sub bit lines arranged in the second direction. The projecting portion has a large-width region having a width greater than the width of each of the sub bit lines in a region in which the memory cells are formed. Therefore, contact portions for connecting the sub bit lines are easily formed at the projecting portions.
In this aspect of the present invention, each of the switching elements may be provided at a position facing the projecting portion of each of the sub bit lines. This enables the switching elements to be easily connected with the projecting portions of the sub bit lines.
In this aspect of the present invention, in each of the block regions, an odd-numbered switching element may be connected to an end portion of an odd-numbered sub bit line on one side, and an even-numbered switching element may be connected to an end portion of an even-numbered sub bit line on the opposite side, among the plurality of the sub bit lines. In this case, the degree of integration of the memory cells can be increased as described later.
In this aspect of the present invention, in two of the block regions adjacent to each other in the first direction, when the switching elements in one block region are referred to as first switching elements and the switching elements in the other block region are referred to as second switching elements, the first and second switching elements commonly connected to one of the main bit lines may be disposed to be adjacent to each other. This enables one impurity layer to be shared by the first and second switching elements, whereby the degree of integration of the memory cells can be increased. In the case where the switching elements are formed using field effect transistors (MOS transistors, for example), source/d
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