Non-volatile semiconductor memory cells

Details Non-volatile semiconductor memory cells Non-volatile semiconductor memory cells

1980-07-07

1983-06-07

Anagnos, Larry N.

Static information storage and retrieval

Systems using particular element

Flip-flop

365185, G11C 1140

Patent

active

043874444

ABSTRACT:
Non-volatile bistable semiconductor latches having a pair of cross-coupled branches, each branch having a complementary driver or load and a driver connected in series at a respective node; at least one of the complementary drivers or loads, or drivers, includes a non-volatile IGFET having a variable threshold voltage (e.g. a FATMOS), said latch additionally including one or more buffer transistors (e.g. P-channel IGFETS) connected between one or both nodes and a latch output line. The buffer transistors increase the predictability of the state of the latch during power-on in a non-volatile mode of operation. Preferably the complementary drivers or loads, and the drivers, are constructed in CMOS or N-channel MOS. The buffers can drive a single DATA output line of twin DATA, DATA lines in a push-pull configuration.

REFERENCES:
patent: 4096398 (1978-06-01), Khaitan
patent: 4132904 (1979-01-01), Harari
patent: 4175290 (1979-11-01), Harari

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