Non-volatile semiconductor memory and process of fabricating...

Details Non-volatile semiconductor memory and process of fabricating... Non-volatile semiconductor memory and process of fabricating...

2006-02-21

2006-02-21

Booth, Richard A. (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

07002204

ABSTRACT:
A non-volatile semiconductor memory including at least one first gate electrode as a floating gate on a semiconductor substrate with intervention of a first insulating film as a tunnel oxide film; sidewall spacers on both sidewalls of the first gate electrode in a direction of a channel length; a bit line formed of an impurity diffusion region of a conductivity type different from the conductivity type of the semiconductor substrate in a surface layer of the semiconductor substrate by the side of the first gate electrode, wherein the bit line comprises a first bit line formed in self-alignment using the first gate electrode as a mask and a second bit line formed in self-alignment using the first gate electrode and the sidewall spacers as a mask.

REFERENCES:
patent: 4267632 (1981-05-01), Shappir
patent: 5151375 (1992-09-01), Kazerounian et al.
patent: 6570214 (2003-05-01), Wu
patent: 1-130570 (1989-05-01), None
patent: 6-181298 (1994-06-01), None
U.S. Appl. No. 10/315,095 filed Dec. 10, 2002 entitled “Non-Volatile Semiconductor Memory and Method of Operating the Same”.
U.S. Appl. No. 10/314,021 filed Dec. 9, 2002 entitled “Non-Volatile Semiconductor Memory and Method of Operating the Same”.
Kume et al; A 1.28m2 Contactless Memory Cell Technology for a 3V-Only 64Mbit EEPROM; IEDM 92, pp. 991-993, 1992.

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