Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-03-13
2004-03-23
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220, C365S185290
Reexamination Certificate
active
06711060
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory having a two-storied gate of a floating gate and a control gate, and methods of driving, operating, manufacturing this memory.
2. Description of the Prior Art
FIG. 26
is a diagram showing a memory cell array configuration in a non-volatile semiconductor memory such as a conventional flash memory, and illustrates a NOR flash memory. In
FIG. 26
, WLm−1 to WLm+1 designate word lines; BLn−1 to BLn+1 designate bit lines; and SL designates a source line.
First, an over-erased condition in the flash memory will be described.
In an array architecture called NOR or DINOR-type in memory cells, there is a difficulty that when there exists a cell in which a threshold voltage Vth (hereinafter, just referred to as Vth) is in a depletion state, i.e. Vth<0 on the same bit line, Vth measurements of the all cells on that bit line cannot be carried out. For example, when the Vth of a cell corresponding to BLn/WLm surrounded by circle A in
FIG. 26
is in a depletion state, even if the threshold voltages Vths of the other cells on the BLn line are in an enhanced condition (Vth>0), the Vths of the other cells cannot be measured since all the Vths become 0 V or less due to an effect of the cell of BLn/WLm.
Hence, when a Vth distribution in the aforementioned array configuration is checked, cells in proportion to the number of cells on the same bit line are determined to have a value of Vth<0 in a Vth distribution of over-erase failure as shown in FIG.
27
. The cells in a depletion condition may cause upon the extraction of electrons from the floating gate of a flash memory when some electrons are accidentally over-extracted.
This phenomenon is described as an erratic over erase in “A Self-Convergence Erase for NOR Flash EEPROM Using Avalanche Hot Carrier Injection” (Document 1: IEEE Trans. Electron Devices, vol.43, p.1937, 1996, S. Yamada et al.).
A write back of the threshold voltage Vth of an over-erased cell will be next described. The write back herein referred to is writing back the Vth of the erased cell to an enhancement condition. Various methods of performing the write back are disclosed in the prior art.
First, a method by channel hot electron (CHE) injection is known as an electron injection to cells in flash memories. Here, the CHE write is a method that high energy electrons accelerated over a barrier height of an oxide are injected into a floating gate among channel electrons accelerated by a steep electric field around the drain of memory cells.
Second, an over-erased bit write back by CHE will be described with a cell structure of conventional NOR flash memories.
FIG. 28
is a schematic cross-section of a flash memory cell for explanation of a conventional over-erased bit write back by CHE. In
FIG. 28
, the reference numeral
11
designates a p-type semiconductor substrate;
12
a
,
12
b
designate n channel source and drain regions, respectively;
13
is a first gate oxide;
14
designates a floating gate made of polycrystalline silicon or polysilicon and the like;
15
designates a three-layered insulating film of oxide, nitride, and oxide, called ‘ONO’ for leakage countermeasure;
16
designates a control gate made of polycrystalline silicon and the like; and Vs, Vd, Vcg, and Vsug designate a source voltage, a drain voltage, a control voltage, and a substrate voltage, respectively. Note that the control voltage Vcg is typically set at a higher value than the drain voltage Vd.
A flash memory employing a CHE method is provided with deeply-doped P+ substrate concentration (~10
18
cm
−3
) and N+ diffused layer (~10
20
cm
−3
) in the vicinity of the drain for enhancement of CHE efficiency. For example,
FIG. 29
is a graph showing an impurity distribution on the channel surface around the drain edge in a conventional cell structure. This shows a change from decrease to increase after a surface position P
0
in which a value of logN plunges. In the conventional cell structure, the CHE efficiency is earned by controlling the expansion of a depletion layer within a p channel substrate region. Referring to the previous Document 1, a drain injection is written As=5×10
15
cm
−2
. The N+ diffused layer concentration after thermal treatment or annealing becomes 10
20
cm
−3
or more in such an injection condition.
Next, the operation will be described.
The cell write is performed in such a manner that high energy electrons or CHE accelerated over the barrier height of the first gate oxide
13
are injected into the floating gate
14
among channel electrons accelerated by a steep electric field around the drain. On the other hand, the cell write back may be performed in such a manner that the threshold voltages Vths of over-erased cells are brought to an enhancement condition by the above CHE method.
However, the following difficulties exist in this method.
(1) Since the over-erased cells have to be selected, the circuit configuration becomes complicated.
(2) Since a Vth variation width to be written is different from that of a conventional write, a desired voltage has to be set for drain/gate. That is, this voltage requires another potential disposition which differs from that typically used to bring cells to a write condition.
(3) A channel current has to be driven upon write back operations. (Id~several tens &mgr;A/cell)
On the other hand, a write back method using a gate current due to Drain Avalanche Hot Electron (hereinafter abbreviated to DAHE) and Drain Avalanche Hot Hole (hereinafter abbreviated to DAHH) is disclosed as a method without performing bit selections in the write back by the above CHE method (see Document 1).
Hereinafter, a cell structure employing such a write back method will be described.
FIG. 30
is a schematic cross-section of a flash memory cell for explanation of a conventional write back of over-erased bits by DAHE/DAHH. In
FIG. 30
, the device configuration is substantially the same as the above memory cell by CHE and the description will be omitted. However, there is a difference in a voltage application to electrodes: GND level is applied to Vcg, while GND level or a negative bias is applied to Vsub.
As shown in
FIG. 31
, the gate current Ig in a cell in flash memories having that drain structure is known in that gate currents specified by DAHH, DAHE, and CHE in turn from a lower side of gate voltages are observed in a gate voltage region in which a channel current flows. This phenomenon is also described in the Document 1 or others (for example, Document 2: IEEE Electron Devices Letter, EDL-7, p.561 (1986), Y. Nissan-Cohen, and Document 3: U.S. Pat. No. 5,546,340, Chung-Yu Hu et al.) Here, the gate current of DAHE/DAHH is that among pairs of electrons and holes generated in a high electric field region near the drain together with “seed” currents flowing in a channel, the electrons or holes accelerated at a high-energy level in said field are injected into a floating gate. The use of that DAHH/DAHE enables to write back over-erased cells self-convergently.
Hereinafter, evaluations in accordance with this write back method will be described.
A cell structure is employed, which has a sectional configuration in
FIG. 32
referring to the aforementioned Document 1.
FIG. 34
is a graph showing results that evaluated in a unit cell the write back by this method.
When a cell over-erased up to about 0 V was left on a condition of drain voltage Vd=5 V and control gate voltage Vcg=0 V, the convergence Vth was written back to about 1.75 V after about 0.1 sec. Thus, the write back method does not require a bit selection which raises an issue in the CHE method, and may be left in such a manner that a drain voltage is applied to all bit lines in an array with a gate voltage of 0 V.
Further, a feature of this method is that even a condition having a Vth higher than the convergence Vth tends to vary toward this convergence Vth. That is, as shown in
Burns Doane Swecker & Mathis L.L.P.
Dinh Son T.
Renesas Technology Corp.
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