Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-11-21
2004-09-07
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185060, C365S185140, C365S185180, C257S315000
Reexamination Certificate
active
06788573
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a non-volatile semiconductor memory and a method of operating the same.
2. Discussion of the Related Art
A semiconductor memory device capable of reading and writing digital data electrically is divided into an EEPROM enabling to program and erase data by a cell unit and a flash memory enabling to erase data only by a block unit over several tens and hundreds bytes and record data by a byte unit.
A conventional EEPROM has been widely used to re-write data by using a small data unit. However, the conventional EEPROM cell includes a pair of transistors. Thus, it occupies a relatively large area. As a result, the conventional EEPROM has a difficulty in realizing a large capacity. In addition, it is fabricated with a high cost.
A memory cell of the conventional flash memory including only one transistor increases an erase unit size instead of reducing a cell size. However, the conventional flash memories have some difficulties in achieving desirable operational characteristics and device reliabilities. Such problems become serious as a design rule is reduced, thereby becoming obstacles or limitations for reducing a cell size.
Such non-volatile memories are fabricated by using various processes to be used for a single memory device. In order to build various functional blocks in SoC (system-on-chip) where the various functional blocks forming a system are integrated on one chip, an EEPROM and a flash memory should be fabricated through the same manufacturing process. In addition, each of the cell sizes thereof should be reduced. Further, they should be operable in low supply voltage.
A non-volatile memory according to a related art is explained by referring to the attached drawings as follows.
FIG. 1A
illustrates a cross-sectional view of a single transistor type flash memory cell according to the related art, and
FIG. 1B
illustrates a layout of the single transistor type flash memory cell of FIG.
1
A.
Referring to
FIG. 1A
, the cell includes a source region
2
and a drain region
3
formed in the surface area of a P-type semiconductor substrate
1
. A channel region will be generated between the source and drain regions
2
and
3
. A gate oxide layer
4
, a floating gate
5
, and a control gate
7
are stacked on the channel region of the substrate
1
. An inter-poly oxide (IPO) layer
6
is formed between the floating and control gates
5
and
7
.
The floating gate
5
stores electric charges therein while the control gate
7
induces a voltage on the floating gate
5
.
The floating and control gates
5
and
7
are formed as a stacked structure, as shown in FIG.
1
A. The source and drain regions
2
and
3
are formed in the semiconductor substrate
1
to be in parallel with both lateral sides of the stacked gates, thereby forming a unit block of a single transistor. A channel hot carrier injection is generally used for a cell programming in this type cell.
Specifically, for the cell programming, about 5V is applied to the drain region
3
. The source region
2
is grounded (0V). About 8V is applied to the control gate
7
. Thus, hot channel electrons are injected into the floating gate
5
.
When an erasing is carried out on the unit block, 0V or a negative high voltage is applied to the control gate
7
while a positive high voltage is applied to the source region
2
or the semiconductor substrate
1
. Thus, a tunneling of the electric charges occurs in the direction of the source region
2
or the semiconductor substrate
1
.
FIG. 1B
illustrates a layout of the flash memory cell having the stacked structure shown in FIG.
1
A.
Referring to
FIG. 1B
, unit cells
11
are separated from each other by a field insulating area
10
. Each control gate
15
of the respective cells is connected to a corresponding word line
12
. The word lines
12
are separated from each other. A bit line
13
is formed in the direction perpendicular to the word line
12
, and each drain region
17
of the respective cells is connected to the bit line
13
through a bit line contact
14
.
Although the single transistor stacked type cell has a reduced cell size, it has serious disadvantages as follows. When erasing data in every non-volatile memory, over-erasure phenomena, a threshold voltage of a cell dropped below 0V during erasing, may take place statistically. On a non-volatile memory with a single transistor staked type cell, if at least one cell in a selected bit line is over-erased, it is unable to read the status of the cells in the same bit line.
Generally, non-uniformity in the manufacturing process and process-induced stress applied to a dielectric layer surrounding the floating gate may cause the over-erasure. A designing technique may solve such an over-erasure problem. Meanwhile, a circuit construction becomes complicated. Therefore, the over-erasure in a single transistor staked type cell should be eliminated at all costs.
In addition, the over-erasure is not allowed in the single transistor stacked type cell and furthermore, an erasing is carried out by the block unit over several tens kilobytes, thereby broadening a statistical threshold voltage distribution of the erased block. Therefore, an actual range of the allowable threshold voltage range becomes much narrower.
An electric charge status in the non-volatile memory cell (i.e., the threshold voltage) corresponds to a logical status of the memory cell. A range of the allowable threshold voltage of the single transistor stacked type cell lies approximately between 1V and 5V.
When a reading voltage of 3.3V is applied to the control gate, a cell current proportional to a difference between 3.3V and 1.0V flows in case that a low level of the threshold voltage is 1V. In the cell programmed with 5V, a current fails to flow since a channel of the cell is blocked.
Therefore, it stores digital data of 1 bit in each cell by reading the current conditions in the following and blocking corresponding to two levels of “1” and “0”, respectively.
Meanwhile, a data reading speed of a memory is proportional to the cell current on the reading. Thus, the speed becomes faster when the cell current is large, while the speed becomes slower when the cell current is small. Therefore, the lower the low level of the threshold voltage is, the larger the cell current is and the faster the reading speed is.
The single transistor stacked type cell according to the related art has a relatively high threshold voltage of over 0V in the low level. Thus, it has a small cell current so that it makes very difficult to improve a reading speed without increasing the read voltage applied to the control gate over the supply voltage level. If the threshold voltage of each memory cell is defined as more than four levels, each of the memory cells enables to store logic data having two bits or more (multi-bits memory). When a programming is carried out with multi-levels, four or more levels of the threshold voltage between the allowable threshold voltages of 1V to 5V should be programmed and read.
In this case, when intervals between the threshold voltage levels become narrower, a reading speed becomes slower and the cell is vulnerable to various noises. Therefore, the intervals in the threshold voltage cannot be reduced further. The wide intervals of the entire allowable threshold voltage range enable to readily realize a multi-bits memory as well as increase a memory speed.
Unfortunately, the single transistor stacked type memory cell having a narrow range of the allowable threshold voltage is unable to realize a reading operation with a high speed and a low voltage. Thus, it is difficult to be implemented as a high-speed multi-bits memory.
Further, the single transistor stacked type cell has much difficulty in reducing a size in accordance with a design rule in the scale under about 0.18 &mgr;m, thereby causing problems/disadvantages in cell characteristics and reliability.
A drain of a floating gate storage transistor, which c
Dinh Son T.
Fleshner & Kim LLP
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