Non-volatile semiconductor memory and method for driving the sam

Details Non-volatile semiconductor memory and method for driving the sam Non-volatile semiconductor memory and method for driving the sam

1991-07-17

1993-05-25

Pascal, Robert J.

Static information storage and retrieval

Read/write circuit

Erase

365185, 36523006, G11C 700, G11C 1100

Patent

active

052146065

ABSTRACT:
In a flash type EEPROM comprising a memory cell matrix, an X decoder and a Y decoder, the X decoder includes a first circuit for charging an output of the first circuit to a voltage supply voltage when the first circuit is selected by an address signal, a depletion N-channel MOS transistor connected between the output node of the first circuit and a corresponding word line and having a gate connected to receive a control voltage, a second circuit for generating a high voltage at an output node of the second circuit at the time of a write mode, and a enhancement P-channel MOS transistor connected between the output node of the second circuit and the corresponding word line and having a gate connected to receive an erase verify signal. In an erase voltage verify mode, the gate of the depletion N-channel transistor is brought to a low level and the enhancement P-channel MOS transistor is turned off, so that a selected word lines is charged through the depletion N-channel MOS transistor. Accordingly, a voltage of the selected word line is set to a level lower than the voltage supply voltage.

REFERENCES:
patent: 4737936 (1988-04-01), Takeuchi
patent: 4823318 (1989-04-01), D'Arrigo et al.
patent: 4860261 (1989-08-01), Kreifels et al.
patent: 5053990 (1991-10-01), Kreifels et al.

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