Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-05-14
2002-05-21
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S333000, C257S506000, C257S510000, C438S257000, C438S279000, C438S426000, C438S439000, C438S702000
Reexamination Certificate
active
06392269
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory, with advanced, device isolating characteristics, which comprises the region of a peripheral circuit and a cell region, on a semiconductor substrate. It also relates to a manufacturing method for the non-volatile semiconductor memory.
2. Description of the Related Art
A conventional method of manufacturing a flash memory will be explained with reference to
FIGS. 1 and 2
.
FIG. 1
shows a configuration of the conventional flash memory, fabricated at the halfway manufacturing stage, just before the step of making an interconnection in a cell region of the flash memory. Source regions and drain regions are both formed in diffused layer regions
301
. Floating gates
303
are formed in hatched regions. Word lines
304
, which also play a role as control electrodes, are formed over the floating gates
303
. Device isolating oxide regions
302
are formed in the regions between the adjacent left and right diffused layers
301
. Tunnel oxides, each playing a role in the generation of a channel region, are formed right under the respective floating gates
303
, but not in the device isolating oxide regions
302
.
The conventional method of manufacturing the flash memory will be explained below, with reference to process cross-sections of FIGS.
2
(
a
) to
2
(
d
), along the line AA′ in
FIG. 1. A
device isolating oxide layers
401
, in
FIG. 2
, correspond to the device isolating oxide layers
302
in FIG.
1
. Floating gates
404
in
FIG. 2
correspond to the floating gates
303
, in FIG.
1
. In FIG.
2
(
b
), the floating gates
404
extend to and exist on the device isolating oxide layers
401
.
Firstly, referring to FIG.
2
(
a
), the device isolating oxide layers
401
, each having a thickness of approximately 400 to 500 nm, are formed on a semiconductor substrate by utilizing the LOCOS (Local Oxidation of Silicon) method, etc., followed by the formation of a tunnel oxide layer
403
, each having a thickness of 10 nm or less, in a device region on the substrate of the flash memory. A polysilicon layer
402
is deposited next, all over the surface. Phosphorous (p), generally, is implanted next, in the polysilicon layer
402
, which has a thickness of approximately 150 nm.
Next, a photo resist (not shown in figures) is patterned by using the conventional photographic process. Thereafter, floating gates
404
are formed by etching the polysilicon layer
402
(see FIG.
2
(
b
)).
Thereafter, an insulation layer
405
is deposited all over the resulting surface of the semiconductor substrate to isolate control gates from the floating gates
404
. The insulation layer
405
with an ordinary, multiple layered structure of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, has a thickness of 18 nm, if it is converted into the thickness of an oxide layer. A polysilicon layer
406
, which is implanted with phosphorous implant, and a silicide layer
407
are deposited next, in the order, all over the substrate (see FIG.
2
(
c
)). Thickness of each of these layers is equal to approximately 150 nm.
Predetermined places in the cell region are covered next, by a resist (not shown in Figures) for etching purposes, so as to form cell gates (hereafter, referred to as “cell gate etching”).
Cell gate etching is then performed. It is noted that no cell gate is formed in any region in the cross-section of FIG.
2
(
d
), since the cross-section is along the line AA′ in FIG.
1
. In this etching step, the silicide layer
407
and the polysilicon layer
406
are both etched and removed in the order. The insulation layer
405
is then etched and removed. Wherein, to remove the insulation layer
405
completely, some extent of over-etching needs to be done. However, the etching selectivity of the insulation layer
405
to the device isolating oxide layer
401
cannot be set to a high value. This causes a partial loss of the device isolating oxide layer
401
, forming concave portions
408
on the respective device isolating oxide layers
401
, as shown in FIG.
2
(
d
).
Thereafter, source regions and drain regions (not shown in Figures) are formed in the cell region, whereas gate regions are also formed in the region of the peripheral circuit. In the region of the peripheral circuit, source regions and drain regions in the transistors are formed. A flash memory is completed next, by subjecting it to an ordinary contact process and an ordinary interconnection process.
However, according to the conventional techniques as described above, there is the problem that concave portions
408
are formed in the device isolating oxide layers
401
of the cell region, due to the fact that the etching selectivity of the insulation layer
405
to the device isolating oxide layer
401
, which is located under the insulation layer
405
, cannot be set to a high value when the insulation layer
405
, in the cell region, is etched (see FIG.
2
(
c
)). This may cause a deterioration of the device isolating property. For example, an ion implant such as an arsenic implant or a phosphorous implant, which is used for the formation of source regions and drain regions, may pass through the concave portions
408
of the device isolating oxide layer, causing the generation of a channel right under each device isolating oxide layer.
SUMMARY OF THE INVENTION
Accordingly, the objective of the present invention is to provide a non-volatile semiconductor memory with advanced, device isolating characteristics and to provide its manufacturing method.
To attain the above objective, according to an aspect of the present invention, a non-volatile semiconductor memory is provided, comprising a plurality of device isolating layers, formed in a semiconductor substrate and a plurality of insulation layers, formed on the respective device isolating layers. An example of the configuration of the non-volatile semiconductor memory, according to the present invention, is illustrated in FIG.
4
(
e
).
According to another aspect of the present invention, a non-volatile semiconductor memory manufacturing method is provided, comprising a first forming step, of forming a plurality of ditches on a layer of floating electrode material, which has been deposited over a plurality of device isolating layers on a substrate, and a second forming step, of forming a plurality of insulation layers, respectively in the plurality of ditches. An example of the process steps of manufacturing the non-volatile semiconductor memory are illustrated in FIGS.
4
(
a
) to
4
(
c
).
According to still another aspect of the present invention, the non-volatile semiconductor memory manufacturing method, further comprises a third forming step, of forming an insulation layer over the resulting surface from the second forming step, and an etching step of etching the insulation layers formed in the third step, the layer of floating electrode material, and the plurality of insulation layers, formed in the third step. An example of the additional process steps, as described above, is illustrated in FIGS.
4
(
d
) and
4
(
e
).
REFERENCES:
patent: 6034393 (2000-03-01), Sakamoto et al.
patent: 62128567 (1987-06-01), None
patent: 265175 (1990-03-01), None
patent: 6-112502 (1994-04-01), None
patent: 6-232374 (1994-08-01), None
patent: 6232374 (1994-08-01), None
patent: 951082 (1997-02-01), None
patent: 9-172152 (1997-06-01), None
NEC Corporation
Wojciechowicz Edward
Young & Thompson
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