Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
1998-11-24
2001-05-29
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S185110
Reexamination Certificate
active
06240032
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to storage devices to be used for computers and portable information devices. More particularly, the present invention relates to electrically erasable programmable non-volatile semiconductor memories, especially to such non-volatile memories storing multi-valued data in each of memory cells thereof.
BACKGROUND OF THE INVENTION
One type of known non-volatile storage devices is erasable programmable read only memories (“EPROMs”). The EPROMs can be programmed (written) by a user.
In order to erase the EPROMs, it is necessary to irradiate the memory cells of the EPROMs with ultraviolet rays. The entire memory cell array is collectively erased by the ultraviolet ray irradiation. For this purpose, the EPROM must be removed from a substrate each time it is rewritten with new data.
Because the EPROMs have a small memory cell area, they are suitable for large capacity storage. The EPROMs, however, require a window-provided package because the data thereof is erased by ultraviolet ray irradiation. Furthermore, because reprogramming is carried out using a writing device called programmer (or writer), the EPROM needs to be removed from the system when writing data.
Conventionally known electrically erasable programmable read only memories (“EEPROMs”) can be electrically reprogrammed within systems in which they are provided. The area of a memory cell of the EEPROMs is, however, about 1.5 to 2 times as large as that of the memory cell of the EPROMs. This results in that the EEPROMs are larger and more costly than the EPROMs. Therefore, it is difficult to provide the EEPROMs with large capacities.
Thus, recently, a memory called “flash memory” (or flash EPROM) has been developed as an intermediate memory between the EPROM and the EEPROM.
The flash memory is a non-volatile semiconductor memory having a function of electrically erasing data of a chip at a time or electrically erasing data of memory cells positioned in a certain region called a sector or a block at a time. The memory cell of the flash memory has an area almost equal to that of the memory cell of the EPROM.
A memory cell, shown in
FIG. 5
, for the flash memory is known from U.S. Pat. No. 5,249,158 and U.S. Pat. No. 5,245,570. The memory cell
501
shown in
FIG. 5
has a floating gate type field effect transistor structure in which one bit (one cell) is composed of one element. Thus, the memory cell
501
can be highly integrated with ease.
Writing data to the memory cell
501
is performed by applying about 12 volts to a control gate electrode
502
, about 7 volts to a drain
503
, and 0 volts to a source
505
to thereby inject hot electrons generated in the vicinity of a drain junction to a floating gate electrode
506
. By the data write, the threshold voltage of the memory cell
501
with respect to the control gate electrode
502
becomes high.
By arranging the memory cell
501
shown in
FIG. 5
to have a multi-value, higher integration will be easily achieved. For example, the memory cell
501
may have a plurality of threshold voltages Vth at which the memory cell takes a 2
n
state at intervals of several hundred millivolts.
In this case, the writing of data to the memory cell
501
is performed by applying 0 volts to the source
505
, pulses of several microseconds to the floating gate electrode
506
at about 12 volts, and pulses of several microseconds to the drain
503
at about 7 volts to thereby inject hot electrons generated in the vicinity of the drain junction to the floating gate electrode
506
.
By the data writing, the threshold voltage Vth of the memory cell
501
with respect to the control gate electrode
502
increases. The threshold voltage Vth can be varied by changing the voltage to be applied to the control gate electrode
502
, the drain voltage or the pulse to be applied to the control gate electrode
502
or the drain
503
.
In order to erase data from the memory cell
501
, the floating gate electrode
506
is grounded and a positive high voltage (about 12 volts) is applied to the source
505
. Thus, high electric field is generated between the floating gate electrode
506
and the source
505
, and electrons stored in the floating gate electrode
506
are drawn to the source
505
by utilizing the tunnel phenomenon through a thin gate oxide film.
Normally, data is erased block by block (for example, in 16K bytes or 64K bytes). The data erasure causes the threshold voltage Vth of the memory cell
501
with respect to the control gate electrode
502
to drop. The memory cell
501
does not have a selection transistor. Thus, when the threshold voltage Vth becomes negative due to excess erasure, a fatal disadvantage that data cannot be correctly read takes place.
When the memory cell
501
stores binary data, the memory cell is read by applying 0 volts to the source
505
, a low voltage about 1 volt to the drain
503
, and about 5 volts to the control gate electrode
502
. The size of a channel current flowing at this time corresponds to information “1” or “0”. Specifically, a larger channel current corresponds to information “1” and a smaller channel current corresponds to information “0”. This fact is utilized for the data reading. The reason a low voltage is applied to the drain
503
is to prevent parasitic write operation (so-called “soft write”) from being performed.
When the memory cell
501
stores multi-valued data, in reading the memory cell
501
, 0 volts is applied to the source
505
, a low voltage of about one volt is applied to the drain
503
, and a voltage to be applied to the control gate electrode
502
is changed. The multi-valued memory data is read by utilizing the value of a voltage applied to the control gate electrode
502
at which voltage the channel electric current flows.
In the memory cell
501
, because writing is executed at the drain side and erasure is executed at the source side, it is preferable to optimize junction profiles individually for each operation. That is, the source
505
and the drain
503
are asymmetric in structure relative to each other; in the drain junction, an electric field convergence type profile is used to enhance writing efficiency; and in the source junction, an electric field relaxation type profile allowing application of a high voltage to the source
505
is adopted.
In the method of applying a high voltage to the source
505
in the erase operation, it is necessary to increase the withstanding voltage in the source junction. Thus, it is difficult to make the structure at the source electrode side fine. Further, hot holes are generated in the neighborhood of the source
505
and a part of the hot holes is trapped inside the tunnel insulation film. Thus, reliability of the cell deteriorates.
As another example of data erasure, negative gate erasing method is known. In this method, a negative voltage (about −10 volts) is applied to the control gate electrode
502
, and a power voltage (about 5 volts) is applied to the source
505
, and data is erased by tunnel electric current. One of the advantages of the negative erasure method is that because a low voltage is applied to the source
505
at a data erasure time, the junction withstanding voltage at the source side is allowed to be low and that it is possible to reduce the length of the gate of the memory cell. Further, the negative erasure method allows the size of a erase block to be small so that data can be erased easily sector by sector.
In the data erasing method of applying a high electric field to the source
505
, tunnel electric current flows between bands and the value of the total electric current of an entire chip is as high as several milliamperes. Thus, it is difficult to use a boosting circuit in the data erasure method. Accordingly, heretofore, an erasing high voltage Vpp is supplied from the outside of the chip.
In the negative gate erasing method, it is possible to supply a power voltage Vcc (5 or 3 volts) to the source
505
. Thus, the negative gate erasure method has an advantage that
Morrison & Foerster
Phan Trong
Sharp Kabushiki Kaisha
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