Non-volatile semiconductor memory

Details Non-volatile semiconductor memory Non-volatile semiconductor memory

1993-03-25

1995-01-24

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Erase

365185, 365900, G11C 700

Patent

active

053847423

DESCRIPTION:

BRIEF SUMMARY
The present invention relates to a non-volatile semiconductor memory, and more particularly to a non-volatile semiconductor memory having a plurality blocks of non-volatile memory cells of two-layered structure, capable of altering data in units of blocks.


BACKGROUND OF THE INVENTION

All-bit flash erase type memories have drawn attention as electrically erasable, programmable read-only memories (E.sup.2 PROM). Recent requirements for such memories are to provide a function for altering data in each of a plurality of memory blocks in units of blocks. For example a 4M bit device is divided into 16 blocks each having 32K bytes or into 4 blocks each having 256K bytes, and data erasure is required to be performed on the blocks per unit basis. With such block division of a cell array, cells in a plurality of different blocks are connected to the same word line or data line. Therefore, repeating write/erase of a particular block may apply stress to cells in other non-selected blocks.
The degree of such stress will be discussed for cells of two-layered structure. In the case of cells of two-layered structure used in a flash type E.sup.2 PROM, data write is performed in a manner similar to EPROM. Namely, a control gate is applied with V.sub.CG =12 V, a drain with V.sub.D =6 V, and a source with V.sub.S =O V. In this state, hot electrons generated by an avalanche effect are injected to the floating gate. For data erase, the control gate is applied with V.sub.CG =0 V, the source with V.sub.S =12 V. In this state, electrons are taken out of the floating gate as F-N tunnel current between the floating gate and source.
The characteristic structure of such a cell resides in that the gate oxide film under the floating gate is about 100 angstroms thinner than that of an EPROM cell because a tunnel current flows between the floating gate and source during data erase, and that the superposing area of the source n.sup.+ region and the floating gate is made wider than that of EPROM.
In a cell array having a plurality of blocks comprised by cells of such structure, stress applied to a cell in an erase state or write state in a non-selected block is shown in Table 1. A cell in an erase state in a non-selected block connected to a selected word line is applied to an electric field of about 7.5 MV/cm between its floating gate and source, and a cell in a write state in a non-selected block connected to a selected data line is applied to an electric field of about 6.5 MV/cm between its floating gate and drain.


TABLE 1 __________________________________________________________________________ Control Floating Gate Drain Source Gate Stress Potential Voltage Voltage Voltage Voltage Difference V.sub.CG V.sub.D V.sub.S V.sub.FG V.sub.FG - V.sub.D V.sub.FG - V.sub.S __________________________________________________________________________ Cell in Erase State 0 V 0 V 0 V 1 V -- -- Cell in Write State 0 V 0 V 0 V -1.2 V -- -- Non-selected Block Erase cell 12 V Open 0 V 7.4 V -- 7.4 V Same Word Line Write cell 12 V Open 0 V 5.2 V -- 5.2 V Non-selected Block Erase cell 0 V 6 V 0 V 3.2 V 2.8 V -- Same Data Line Write cell 0 V 6 V 0 V -0.4 V 6.4 V -- __________________________________________________________________________
Next, there will be discussed the time period while stress is applied to a cell in a non-selected block during data erase or data write. Consider a 4M bit device divided into blocks at intervals of 32K bytes in the data line direction. Assuming that cells in a block are subject to write/erase as many as 10.sup.5 times with a write time of 10 .mu.s and write occurrence frequency of 25 times for each cell, a cell in a non-selected block is applied with V.sub.CG =12 V during the total time period of 800 sec. Stress of 7.5 MV/cm is therefore applied between the floating gate and source during the time period 800 sec, inevitably leading to write error. As an alternate, consider a 4M bit device divided into blocks at intervals of 32K bytes in the word

REFERENCES:
patent: 5051953 (1991-09-01), Kitazawa et al.
patent: 5103425 (1992-04-01), Kuo et al.
patent: 5109361 (1992-04-01), Yim et al.
IEEE International Solid-State Circuits Conference, Feb. 1989, No. 32, pp. 132-133, 313, "A 5V only 256K Bit CMOS Flash EEPROM", D'Arrigo et al.
Patent Abstracts of Japan, vol. 13, No. 146 (P-854), 11, Apr. 1989, 63-308797, Dec. 16, 1988.
"A 1Mb FLASH EEPROM", Raul-Adrian Cernea et al., IEEE International Solid-State Circuit Conference 1989, pp. 138-139.

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