Non-volatile semiconductor memory

Details Non-volatile semiconductor memory Non-volatile semiconductor memory

2002-05-06

2004-09-07

Tran, Thien F (Department: 2811)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S230030

Reexamination Certificate

active

06788600

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor memory and more particularly to a non-volatile semiconductor memory such as a non-volatile flash memory that may have an improved layout freedom.
BACKGROUND OF THE INVENTION
It is a continuing goal to improve layout freedom of semiconductor devices. By doing so, chip size may be reduced and thus, manufacturing costs may be reduced.
FIG. 9
is a block diagram illustrating a plan view of a conventional non-volatile flash memory and given the general reference character
900
.
Conventional non-volatile flash memory
900
is divided into two banks (B
0
and B
1
). Bank B
0
has four memory cell arrays (MCA
00
to MCA
03
) arranged in quadrants to form a rectangular shape in a plan view. Bank B
1
has four memory cell arrays (MCA
10
to MCA
13
) arranged in quadrants to form a rectangular shape in a plan view. Each memory cell array (MCA
00
to MCA
03
and MCA
10
to MCA
13
) contains 512 local bit lines LB and 512 word lines (not illustrated in FIG.
9
). Memory cells are formed at intersections of bit lines LB and word lines.
Bank B
0
has main X decoders (XDEC
10
, XDEC
11
, and XDEC
20
), and sub X decoders (XSUB
00
to XSUB
03
) that are used to select a word line. Bank B
1
has main X decoders (XDEC
12
, XDEC
13
, and XDEC
21
), and sub X decoders (XSUB
10
to XSUB
13
) that are used to select a word line. Each memory cell array (MCA
00
to MCA
03
and MCA
10
to MCA
13
) has a switch group (Y
1
S
0
to Y
1
S
3
) located at ends of bit lines LB and connect local bit lines LB to main bit lines MB. A driver (Y
1
D
0
to Y
1
D
3
) is adjacent to and drives a switch group (YS
0
to YS
3
). A switch group (Y
3
S
0
and Y
3
S
1
) is located between sense amplifier blocks SAB and main bit lines MB. A driver (Y
3
D
0
and Y
3
D
1
) is located next to and drives a switch group (Y
3
S
0
and Y
3
S
1
).
Referring now to
FIG. 10
, a circuit schematic diagram illustrating memory cell arrays (MCA
00
to MCA
03
) of bank B
0
is set forth.
In order to avoid unduly cluttering the figure,
FIG. 10
only illustrates sixteen local bit lines LB and four main bit lines MB for each memory cell array (MCA
00
to MCA
03
) of bank B
0
. Actually, each memory cell array (MCA
00
to MCA
03
) has 512 local bit lines LB and there are 128 main bit lines MB disposed over each memory cell array (MCA
00
to MCA
03
).
As illustrated in
FIG. 10
, memory cells MC are formed at intersections of local bit lines LB and word lines WL. Switch group Y
1
S
0
includes transistors Tr
1
. Every other local bit line LB in memory cell arrays (MCA
00
and MCA
01
) has an end connected to a transistor Tr
1
. Switch group Y
1
S
1
includes transistors Tr
2
. Every other local bit line LB in memory cell arrays (MCA
00
and MCA
01
) has an upper end connected to a transistor Tr
2
. In this way, every local bit line LB has a lower end connected to a transistor (Tr
1
or Tr
2
) in a switch group (Y
1
S
0
and Y
1
S
1
). In switch group Y
1
S
0
, two transistors Tr
1
are connected to a main bit line MB. In switch group Y
1
S
1
, two transistors Tr
2
are connected to a main bit line MB. In this way, one of four local bit lines LB are selectively connected to one main bit line MB through switch groups (Y
1
S
0
and Y
1
S
1
).
Gates of transistors Tr
1
in each switch group Y
1
S
0
are connected to a driver Y
1
D
0
through signal lines (D
10
and D
11
). Signal line D
10
is connected to the gate of one-half of transistors Tr
1
in switch group Y
1
S
0
. Signal line D
10
is connected to the gate of the other one-half of transistors Tr
1
in switch group Y
1
S
0
. Switch groups (Y
1
S
1
to Y
1
S
3
) are arranged in a similar manner. Drivers (Y
1
D
0
to Y
1
D
3
) are respectively arranged between adjacent switch groups (YLS
0
to Y
1
S
3
).
Switch group Y
3
S
0
is disposed between main bit lines MB and sense amplifier blocks SAB. Switch group Y
3
S
0
includes transistors Tr
4
. Each main bit line MB is connected to a source/drain of a transistor Tr
4
. The other source/drain of transistor Tr
4
is connected to a sense amplifier SA in sense amplifier block SAB. Driver Y
3
D
0
is commonly connected to gates of transistors Tr
4
through signal line D
30
. Although only four transistors Tr
4
are illustrated in each switch group Y
3
S
0
, there are
128
transistors Tr
4
in each switch group or one transistor Tr
4
for each main bit line MB. Bank B
1
is similarly configured as bank B
1
. In bank B
1
switch groups Y
3
S
1
include transistors Tr
4
having gates commonly connected to a driver Y
3
D
1
through a signal line.
Referring now to
FIG. 9
, a DQ pad PAD
1
is provided as a data I/O terminal and is connected to each sense amplifier block SAB. An input pad PAD
2
receives an address signal and control signal. Conventional non-volatile flash memory
900
also includes a peripheral circuit P
1
(an address buffer, for example), a peripheral circuit P
2
(a power source generation circuit, for example), and a peripheral circuit P
3
(such as a read-out and write-in control circuit, for example).
In conventional non-volatile flash memory
900
, memory cell arrays (MCA
00
, MCA
01
, MCA
10
, and MCA
11
) can be simultaneously accessed because each memory cell array (MCA
00
, MCA
01
, MCA
10
, and MCA
11
) is connected to 128 sense amplifiers SA in sense amplifier block SAB. The 512 sense amplifiers SA in the four sense amplifier blocks SAB can then output data via DQ pad PAD
1
.
In conventional non-volatile flash memory
900
, the 512 sense amplifiers SA are arranged in a row along the word line direction. Accordingly, the layout can be restricted in this area. As an example, because each main bit line MB is connected to a sense amplifier SA in sense amplifier block SAB, the sense amplifier SA must have a layout pitch no greater than the pitch of adjacent main bit lines MB.
In view of the above discussion, it would be desirable to provide a semiconductor memory device such as a non-volatile semiconductor memory that may have an increased layout freedom.
SUMMARY OF THE INVENTION
According to the present embodiments, a non-volatile flash memory that may have an improved layout freedom is disclosed. A non-volatile flash memory may include a plurality of banks. Each bank may include a plurality of memory cell arrays including a plurality of memory cells connected to sub bit lines. A plurality of sub bit lines may be selectively connected to a main bit line by a group switch. A group of main bit lines may be disposed over a memory cell array. A group of main bit lines may be selectively connected to a sense amplifier block by a group switch group and a bank switch group. In this way, a sense amplifier block may be shared by a plurality of groups of main bit lines. In this way, layout freedom may be improved.
According to one aspect of the embodiments, a non-volatile semiconductor memory device may include a first and second bank. Each bank may include a first and second memory cell array. Each of the first and second memory cell array may include n×k sub bit lines. N first main bit lines may be disposed over the first memory cell array. Each first main bit line may be coupled to k sub bit lines in the first memory cell array by a first sub bit line selecting circuit. N second main bit lines may be disposed over the second memory cell array. Each second main bit line may be coupled to k sub bit lines in the second memory cell array by a second sub bit line selecting circuit. A first sense amplifier block may include n sense amplifiers. A first main bit line selecting circuit may be coupled between the n first main bit lines of the first bank and the first sense amplifier block. A second main bit line selecting circuit may be coupled between the n second main bit lines of the first bank and the first sense amplifier block. The first main bit line selecting circuit may provide an electrical connection between each of the n first main bit lines of the first bank and a corresponding one of the n sense amplifiers when enabled. The second main bit line s

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