Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-10-10
2002-08-27
Flynn, Nathan J. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000
Reexamination Certificate
active
06441425
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a non-volatile semiconductor device, and in particular, to a non-volatile semiconductor device for inputting and outputting multi-value information for one memory cell.
Referring to FIG.
1
through
FIG. 3
, description will be made about a structure of a related non-volatile memory cell.
Generally, when multi-value information of one bit or more is stored for a non-volatile memory cell, many kinds of threshold values are prepared for a channel portion of a transistor.
During a reading operation, the kind of the threshold value given to the memory cell is detected, and the multi-value information is obtained by logically calculating the detected result.
Referring to
FIG. 4
, description will be made about an example of a reading operation when 2-bit information is stored for one memory cell.
Four kinds of threshold values are prepared as VT
0
, VT
1
, VT
2
, and VT
3
to store the 2-bit information for the memory cell.
On the other hand, setting values of gate voltages are defined as VWD
1
, VWD
2
and VWD
3
, respectively. In this event, the relationship between the gate voltages and the threshold values is defined as the following equation (1).
0
<VT
0
<
VWD
1
<
VT
1
<
VWD
2
<
VT
2
<
VWD
3
<
VT
3
(1)
Further, a sense-amplifier circuit detects an ON state when a current flows through the memory cell while it detects an OFF state when no current flows through the memory cell.
Now, it is assumed that the threshold value of the memory cell to be read is defined as VT
1
.
First, the gate voltage is set to VWD
1
in a first reading operation. At this time, the memory cell is not in a conductive state because the threshold value of the memory cell is equal to VT
1
. Accordingly, the judgement becomes OFF.
Subsequently, the gate voltage is set to VWD
2
in a second reading operation. Consequently, the gate voltage reaches a higher level than the threshold value VT
1
in the memory cell, and the memory cell is put into the conductive state. As a result, the judgement becomes ON.
Next, the gate voltage is set to VWD
3
in a third reading operation. In this case, the judgement also becomes ON.
The above-mentioned judgement results of the first to third reading operations are logically calculated to determine an output data.
As illustrated in
FIG. 5
, output information (OUT DATA) is assigned for the threshold value of each memory cell. Thereby, 2-bits information is stored for one memory cell.
Similarly, description will be made about such a case that 4-bits information is stored for one memory cell with reference to
FIGS. 6 and 7
.
When 4-bits output information is stored, the number of the threshold values of the memory cell is equal to
16
, and the reading number (namely, the gate switching number) is equal to 15.
In general, when the conventional non-volatile memory has the multi-value n, the necessary threshold number (NTV) and the gate voltage switching number (GNV) are represented by the following equations, respectively.
NTV=n
2
(2)
GNW=NTV
−1 (3)
More specifically, when the output information to be stored for one memory cell is changed from 2 bits to 4 bits, the threshold number is changed from 4 to 16. At the same time, the reading number is changed from 3 to 15.
To this end, it is actually impossible to store further more output information in the conventional non-volatile memory cell.
Moreover, when ON bits continuously appears along the same word line (gate) direction in the memory cell illustrated in
FIGS. 1 through 3
, a current (IL
1
) inevitably flows in a direction of an adjacent cell even when a selective memory has an OFF bit.
In this event, the ON bit corresponds to a cell which can flow the current while the OFF bits corresponds to a cell which can not flow the current.
To solve such a problem, a pre-charge technique is necessary to read out the OFF bit. Consequently, the conventional non-volatile semiconductor device must have a complex logic circuit for the pre-charge. As a result, the number of devices constituting the apparatus becomes high.
In addition, even the pre-charge is carried out, the current (IL
1
) is not completely eliminated. This phenomenon prevents an accurate operation of the sense-amplifier circuit for detecting a fine current.
Further, the threshold value is set by implanting ions into the memory cell illustrated in
FIG. 1
, and the number of diffusion layers (BN) for which the sense amplifier circuit charges by the information (threshold value) of the adjacent cell with respect to the selective cell is different. Thereby, the difficulty of transient design inevitably increases.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide to a non-volatile semiconductor device which is capable of reducing the switching number of a gate voltage by decreasing the necessary number of threshold values when a multi-value information is read out from the non-volatile memory cell.
It is another object of this invention to provide a non-volatile semiconductor device in which a pre-charge technique is not required.
It is still another object of this invention to provide a non-volatile semiconductor device which is capable of reducing the difficulty of transient design of the non-volatile semiconductor device using a multi-value technique.
According to this invention, a non-volatile semiconductor device stores multi-value information of at least two bits in one memory cell.
In this case, a source region and a drain region serve as diffusion regions. Further, a first channel region and a second channel region are placed between the source region and the drain region.
A first gate electrode is arranged over the first channel region and the drain region. A second gate electrode is arranged over the second channel region and the source region.
With such a structure, the first channel region stores a first threshold value while the second channel region stores a second threshold value different from the first threshold value.
In this event, the first and second threshold values may be independently given to the first and second channel regions by implanting ions.
Herein, the first and second threshold values are independently given to the first and second channel regions in a order to produce combinations of the first and second threshold values as the multi-value information.
According to this invention, a non-volatile semiconductor memory device stores multi-value information of at least two bits in one memory cell.
In this case, a plurality of first word lines are placed in a horizontal direction while a plurality of diffusion layers are placed in a perpendicular direction for the first word lines.
Further, a plurality of second word lines are alternately placed so as to cover the diffusion layers.
A first channel region is arranged under the first word line and between adjacent diffusion lines and stores a first threshold value.
On the other hand, a second channel region is arranged under the second word line and between the adjacent diffusion lines and stores a second threshold value different from the first threshold value.
Moreover, a sense amplifier is coupled to at least one of the diffusion layers and produces combinations of the first and second threshold values as the multi-value information.
With this structure, each of the diffusion lines has a first width while each of the second word lines has a second width.
Under such a circumstance, the second width may be wider than the first width.
Further, a ground is preferably coupled to at least one of the diffusion lines.
In this event, the diffusion line serves as any one of a source region and a drain region while the first word line serves as a first gate electrode over the drain region and the first channel region. Further, the second word line serves as a second gate electrode over the source region and the second channel region.
The first and second threshold values may be independently given to the first and second channel regions by imp
Flynn Nathan J.
Hutchins, Wheeler & Dittmar
NEC Corporation
Quinto Kevin
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