Non-volatile semiconductor device

Static information storage and retrieval – Read/write circuit – Erase

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365185, 365900, G11C 1300

Patent

active

054266114

ABSTRACT:
When each of memory transistors 1-4 is to be selected for erasure, word lines WL1 and WL2 are set at GND level, source lines SL1 and SL2 are set at high-potential level, and bit lines BL1 and BL2 are set at open level. On selection of the memory transistors for nonerasure, the word lines WL1 and WL2 are set at high-potential level, the source lines SL1 and SL2 are set at open level and the bit lines BL1 and BL2 are set at open level. The selection is carried out by switching word line signals. The erase operation can be stopped by detecting the threshold voltage in the memory transistors 1-4. After the erase operation has been stopped, the threshold voltage in the memory transistors can be monitored and verified.

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patent: 5247478 (1993-09-01), Gupta et al.
patent: 5274599 (1993-12-01), Ema
patent: 5287317 (1994-02-01), Kobayashi et al.

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