Non-volatile programmable read only memory device having memory

Static information storage and retrieval – Floating gate – Particular biasing

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36518911, 365218, 36523006, 257314, 257316, 257324, G11C 1134, G11C 700

Patent

active

052745872

ABSTRACT:
An electrically erasable and programmable read only memory device comprises a plurality of series combinations of memory cells arranged in rows and columns, bit lines each coupled to the front memory cells of the series combinations in one of the columns, a source line coupled to the rearmost memory cells of the plurality of series combinations, and word lines associated with the row of the memory cells, wherein each of the memory cells is implemented by a parallel combination of a floating gate type memory transistor and a switching transistor coupled to first and second word lines, respectively, so that any memory cell is rewriteable without simultaneous erasing operation on the series combination.

REFERENCES:
patent: 4630089 (1986-12-01), Sasaki et al.
patent: 4633438 (1986-12-01), Kume et al.
patent: 4667217 (1987-05-01), Janning
patent: 5060034 (1991-10-01), Shimizu et al.

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