Non-volatile programmable memory having a buffering capability a

Details Non-volatile programmable memory having a buffering capability a Non-volatile programmable memory having a buffering capability a

1997-09-29

1999-01-19

Dinh, Son T.

Static information storage and retrieval

Addressing

Byte or page addressing

36518523, 36518905, G11C 700

Patent

active

058620990

ABSTRACT:
A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustratively a serial device connected to the serial port of the microcontroller. The memory device includes a page latch load circuit which provides serial I/O to the microcontroller and transfers I/O bits in a predetermined order to/from the page latches. Page latches are connected over many bit lines to a memory cell array. The page latches not only supports programming and reading of sectors in the memory cell array, but also provides one or more of the following functions: directly accessible to the microcontroller as an SRAM scratch pad, directly loadable from the memory cell array to facilitate single byte "read-modify-write" operations, and loadable during programming operations to support real time applications.

REFERENCES:
patent: 5222040 (1993-06-01), Challa
patent: 5291584 (1994-03-01), Challa et al.
patent: 5347487 (1994-09-01), Dao et al.
patent: 5355335 (1994-10-01), Katsuno
patent: 5361229 (1994-11-01), Chiang et al.
patent: 5410680 (1995-04-01), Challa et al.
patent: 5414658 (1995-05-01), Challa
patent: 5535159 (1996-07-01), Nii
Bauer et al., TA7.7: A Multilevel-Cell 32 Mb Flash Memory, 1995 IEEE International Solid-State Circuits Conference, Feb. 16, 1995, pp. 132-133.
Cernea et al., TA7.4: A 34Mb 3.3V Serial Flash EEPROM for Solid-State Disk Applications, 1995 IEEE International Solid-State Circuits Conference, Feb. 16, 1995, pp. 126-127.
Imamiya et al., TA7.6: A 35ns-Cycle Time 3.3V-Only 32 Mb NAND Flash EEPROM, 1995 IEEE International Solid-State Circuits Conference, Feb. 16, 1995, pp. 130-131.
Kobayashi et al., TA7.2:A 3.3V-Only 6Mb DINOR Flash Memory,1995 IEEE International Solid-State Circuits Conference, Feb. 16, 1995, pp. 122-123.
Mills et al., TA7.1: A 3.3V 50MHz Synchronous 16Mb Flash Memory, 1995 IEEE International Solid-State Circuits Conference, Feb. 16, 1995, pp. 120-121.
Nozoe et al., TA7.3: A 3.3V High-Density and Flash Memory with 1 ms/512B Erase & Program Time, 1995 IEEE International Solid-State Circuits Conference, Feb. 16, 1995, pp. 120-121.
Pathak & baker, Session 7 Overview: Flash Memory, 1995 IEEE International Solid-State Circuits Conference, Feb. 16, 1995, p. 11.
Suh et al., TA7.5 A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme, 1995 IEEE International Solid-State Circuits Conference, Feb. 16, 1995, pp. 128-129.

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