Non-volatile product term (pterm) cell

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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C326S046000, C365S154000

Reexamination Certificate

active

06963222

ABSTRACT:
A non-volatile product term cell is provided having a first floating gate located over a first p-channel transistor and a first n-channel transistor, and a second floating gate located over a second p-channel transistor and a second n-channel transistor. A control gate is located over the first and second floating gates. A first tunnel oxide capacitor is coupled to the first floating gate and a second tunnel oxide capacitor is coupled to the second floating gate. A first transistor pair is coupled between the first p-channel transistor and the second n-channel transistor, and a second transistor pair is coupled between the second p-channel transistor and the first n-channel transistor. The first and second floating gates are programmed and/or erased. Complementary input signals are applied to the first and second transistor pairs. An output signal is provided in response to the programmed/erased states of the first and second floating gates.

REFERENCES:
patent: 4809225 (1989-02-01), Dimmler et al.
patent: 5101378 (1992-03-01), Radjy et al.
patent: 5742542 (1998-04-01), Lin et al.
patent: 6294809 (2001-09-01), Logie
patent: 6738281 (2004-05-01), Yokozeki
patent: 6822894 (2004-11-01), Costello et al.
patent: 6836428 (2004-12-01), Nakura et al.

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