Non-volatile memory with test rows for disturb detection

Details Non-volatile memory with test rows for disturb detection Non-volatile memory with test rows for disturb detection

2005-02-08

2005-02-08

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S196000

Reexamination Certificate

active

06853598

ABSTRACT:
A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and reading operations. Test rows of memory cells are provided in the array to allow for memory cell disturb conditions. The test rows are not externally accessible for standard program and read operations. The test rows are located near bit line driver circuitry to insure the highest exposure to bit line voltages that may disturb memory cells in the array.

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U.S. Appl. No. 09/943480.

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