Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-08-30
2003-07-22
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S196000
Reexamination Certificate
active
06597609
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory devices and leakage detection.
BACKGROUND OF THE INVENTION
Electrically erasable and programmable read only memories (EEPROMs) are reprogrammable non-volatile memories that are widely used in computer systems for storing data. The typical data storage element of an EEPROM is a floating gate transistor, which is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source and drain regions. Data is represented by charge stored on the floating gate and the resulting conductivity obtained between source and drain regions.
For example, a floating gate memory cell can be formed in a P-type substrate with an N-type diffused source region and an N-type drain diffusion formed in the substrate. The spaced apart source and drain regions define an intermediate channel region. A floating gate, typically made of doped polysilicon, is located over the channel region and is electrically isolated from the other cell elements by oxide. For example, a thin gate oxide can be located between the floating gate and the channel region. A control gate is located over the floating gate and can also be made of doped polysilicon. The control gate is separated from the floating gate by a dielectric layer.
To program a memory cell, a high positive voltage Vg, such as +12 volts, is applied to the control gate of the cell. In addition, a moderate positive voltage of about +6 to +9 volts is applied to the drain (Vd) and the source voltage (Vs) is at ground level, as is a substrate voltage (Vsub). In prior memories, the current requirements for the +12 volts applied to the control gate and the +6 to +9 volts applied to the drain region are relatively small. This is due in large part to the fact that only a few flash cells are ever programmed at one time; thus, these voltages can be generated on the integrated circuit utilizing charge pump circuitry that is powered by the primary supply voltage Vcc. The above voltage ranges are based upon the assumption that the primary supply voltage Vcc for the memory is +5 volts.
The above conditions result in the inducement of hot electron injection in the channel region near the drain region of the memory cell. These high-energy electrons travel through the thin gate oxide towards the positive voltage present on the control gate and collect on the floating gate. The electrons remain on the floating gate and function to increase the effective threshold voltage of the cell as compared to a cell that has not been programmed. The memory cells can be erased to remove the floating gate charge. Erase operations are typically performed simultaneously on a block of memory cells of a flash memory device. During an erase operation, one of the blocks is selected. In one embodiment, the un-selected blocks remain coupled to common bit lines, the unselected blocks are subjected to the erase voltage coupled to the selected bit line. These erase voltages can disturb the memory cells in the un-selected blocks. A time consuming process of checking the memory cells in the un-selected blocks is typically performed to identify cells that required repair.
Further, as memory cell population densities increase, the physical space allocated to device components decreases. For example, bit lines used to couple memory cells located in a column of the memory device may increase in length and decrease in width. These changes in the bit lines result in an increased resistance for the bit line. As such, programming speeds of some memory cells may increase as a result of slower propagation times. Further, bit line driver circuits must be able to provide higher program voltages to overcome the increased voltage drop along bit lines as a result of the increased resistance.
During an erase operation, the gate is grounded or brought to a negative voltage, while the source is brought to a high voltage, such as 6 or 10 volts. The drain of the cells is left floating and will typically go to a voltage around 3 volts due to source to drain leakage. In another embodiment, often called “channel erase” (as opposed to “source erase” described above), the gate is brought negative while the source, the substrate of the cell and/or the drain are brought high. In this case, the drain, or bit line voltage will be at the same value as the source, about 6 volts.
In both cases, the bit lines will be at a positive voltage. In a memory where common bit lines are shared across erase blocks, this positive voltage will create a disturb situation. In this disturb situation, memory cells in an un-selected block see 3 to 6 volts on their drain, while their source and gate are grounded. This condition, called drain disturb, results in a lowering of cell threshold voltage of the disturbed cells which affects the data stored in the cells if the data stored was a “0” (programmed state).
A similar condition appears during a program operation, where the bit line will be at 6V, and therefore the cells sharing this bit line in unselected blocks will have their drains at 6V, and their sources and gates grounded. During a program operation the cells located closest to the data driver will see the highest drain voltage since the voltage drop from the data driver to cells is least. During an erase operation no current flows in the bit lines, so the drain voltage will be similar on all cells.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a disturb detection in a non-volatile memory device.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a non-volatile memory device comprises an array of non-volatile memory cells arranged in rows and columns, a plurality of bit lines coupled to the non-volatile memory cells, a driver circuit coupled to the plurality of bit line, and test rows coupled to the array and located near the driver circuit.
In another embodiment, a flash memory device comprises an array of floating gate non-volatile memory cells arranged in rows and columns, a bit line coupled to the non-volatile memory cells, and first and second driver circuits respectively coupled to first and second end regions of the bit line. A decoder circuit is provided to selectively couple the first and second driver circuits to the bit line. First and second sets of addressable memory cell test rows are coupled to the array and respectively located near the first and second driver circuits.
A method of erasing memory cells in a non-volatile memory device is provided. The method comprises initiating an erase operation on memory cells located in a first part of an addressable array of memory cells, and performing a disturb test operation on test rows to forecast if memory cells located in a second part of the addressable array of memory cells were disturbed during the erase operation.
Another method of operating a non-volatile memory system comprises initiating an erase operation on memory cells located in a first block of an array of memory cells of a memory device in response to instructions from an external processor, performing a disturb test operation on test rows to forecast if memory cells located in additional blocks of the array were disturbed during the erase operation, and performing a data recovery operation on the memory cells located in the additional blocks of the array based upon the disturb test operation.
The invention further provides methods and apparatus of varying scope.
REFERENCES:
patent: 5299147 (1994-03-01), Holst
patent: 5487044 (1996-01-01), Kawaguchi et al.
patent: 5490110 (1996-02-01), Sawada et al.
patent: 5572692 (1996-11-01), Mur
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
Tran M.
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