Non-volatile memory with temperature-compensated data read

Details Non-volatile memory with temperature-compensated data read Non-volatile memory with temperature-compensated data read

2001-11-02

2003-05-06

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189090, C365S185220

Reexamination Certificate

active

06560152

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to non-volatile memories, and in particular to a non-volatile memory with a temperature-compensated data read cycle.
BACKGROUND OF THE INVENTION
A popular non-volatile memory system is a flash electrically erasable, programmable read only memory (EEPROM). Individual cells of such a memory typically include one or more storage elements that store a variable amount of static charge. The storage elements are most commonly conductive floating gates, so this is the example primarily described herein, but can also be areas of a charge trapping dielectric. The level of charge stored by the floating gate represents the data value stored by the data storage element. The floating gate typically overlies a channel region of a transistor.
Data is read from a storage location by applying a voltage to a control gate overlying the floating gate. The level of charge stored by the floating gate, in combination with the voltage applied to the control gate, determines whether the transistor will conduct current through its channel. The level of charge stored by the floating gate can therefore be determined by either measuring that current or finding the control gate voltage required to make the transistor conduct. In either case, the measured quantity is compared with reference levels in order to determine the state of the cells.
Binary state memory cells may be used in flash memories. These memory cells have two states: “programmed” (usually representing a one) and “erased” (usually representing a zero). However, such cells do not efficiently use the valuable real estate of the integrated circuit, since only one bit of information is stored per floating gate. Many flash memories therefore use multiple charge levels (more than two) for the floating gates, so that each floating gate may store more than one bit of information.
As the number of charge level states of the operation of individual floating gates increases, the voltage difference between the states necessarily decreases. The increasing proximity of the voltage level ranges of an increased number of states makes discerning one state from another more difficult.
Because the operating characteristics of the memory cell transistors change with temperature, the control gate voltage required to turn on the transistor also varies with temperature, even as the charge level carried by the floating gate remains unchanged. This thermal variation can result in inaccurate reading of data from memory cells, due to the close proximity of the voltage levels of the floating gate.
One technique to compensate for the effects of such temperature variations is to include reference memory cells, formed in the same manner as the data storage cells and on the same integrated circuit chip, that provide the reference levels against which the measured currents or voltages of the memory cells are compared in order to read their storage states. The reference cells are therefore affected in the same manner by temperature variations of the circuit chip as are the memory storage cells. The reference levels then move with temperature in the same manner as the values read from the memory cells. This technique is described in U.S. Pat. No. 5,172,338, which patent is incorporated herein by this reference.
Other techniques use a device other than a memory cell as a temperature reference. A band gap device is an example of such a device that can be provided on the same chip as the storage cells or elsewhere in thermal communication with such a chip. Voltages applied to control gates of the memory cells have been controlled in this manner.
SUMMARY OF THE INVENTION
The present invention, briefly and generally, provides a technique for temperature compensated reads of non-volatile memory cells by varying a bit-line voltage or current in response to changing temperature. The invention is implemented in one form by providing a circuit on the memory cell array chip that, during a read operation, automatically biases a voltage or current applied to the cells' source or drain terminal by an amount that compensates for a changing threshold voltage characteristic of the memory cells that is caused by a changing temperature of the circuit chip.
In one embodiment, the non-volatile memory includes a storage resistor having a data storage element such as a floating gate, one or more control gates and first and second source/drain terminals. A current source provides a current to the first source/drain terminal of the data storage element. A node is electrically connected to the second source/drain terminal of the data storage element. A bias circuit provides a bias voltage to the node. The bias voltage varies with temperature in a manner approximately inverse to the thermal variation of the threshold voltage of the data storage transistor. A control gate voltage circuit provides a controlled voltage level to the control gate(s) of the data storage transistor.
In a more specific embodiment, a method of reading stored data from a non-volatile memory includes providing a current to a first source/drain terminal of an EEPROM transistor which has a second source/drain terminal coupled to a node. The method further includes drawing a current from the node by a current source and providing a thermally invariant bias voltage to a gate of a transistor which has a source or drain terminal coupled to the node. The transistor conducts at least a portion of the current. The method also includes providing a voltage to a control gate of the EEPROM transistor and detecting a voltage at the first source/drain terminal of the EEPROM transistor.
An advantage of the present invention is that the temperature of the memory cell does not affect the data value read from the memory cell transistor. Another advantage of the present invention is that temperature compensation is achieved with the use of minimal additional circuitry, thus taking less space on the memory chip.


REFERENCES:
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 6205074 (2001-03-01), Van Buskirk et al.
patent: 2000011671 (2000-01-01), None

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