Non-volatile memory with induced bit lines

Details Non-volatile memory with induced bit lines Non-volatile memory with induced bit lines

2005-04-12

2005-04-12

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S288000, C438S216000, C438S261000, C438S591000, C438S593000

Reexamination Certificate

active

06878988

ABSTRACT:
An electrically programmable non-volatile memory cell is provided. A semiconductor substrate is prepared. A pair of spaced apart source/drain (S/D) regions is defined on the semiconductor substrate. The spaced apart S/D regions define a channel region in between. A first dielectric layer such as silicon dioxide is disposed on the S/D regions. An assistant gate is stacked on the first dielectric layer. The assistant gate has a top surface and sidewalls. A second dielectric layer comprising a charge-trapping layer is uniformly disposed on the top surface and sidewalls of the assistant gate and is also disposed on the channel region. The second dielectric layer provides a recessed trough between the S/D regions. A conductive gate material fills the recessed trough for controlling said channel region.

REFERENCES:
patent: 6436768 (2002-08-01), Yang et al.
patent: 20030006450 (2003-01-01), Haspeslagh

Affiliated with

Also associated with

Rating

Non-volatile memory with induced bit lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-volatile memory with induced bit lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile memory with induced bit lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3436206