Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-09-28
2001-09-04
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S065000
Reexamination Certificate
active
06285577
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile memory, and more particularly to a composite non-volatile memory including a ferroelectric capacitor and an MFS (metal-ferroelectric-semiconductor) field effect transistor, MFIS (metal-ferroelectric-insulator-semiconductor) field effect transistor or MFMIS (metal-ferroelectric-insulator-semiconductor) field effect transistor.
2. Description of the Related Art
The ferroelectric memory which is being researched nowadays is roughly classified into two systems. The one is a memory of a system in which the quantity of inverted charges of a ferroelectric capacitor is detected. This system includes a ferroelectric capacitor and a select transistor.
The other is a memory of the system in which a change in the resistance of semiconductor due to spontaneous polarization of ferroelectric is detected. A representative system thereof is an MFSFET. This MFSFET has a MIS structure using ferroelectric for a gate insulating film. In this structure, a ferroelectric layer must be directly formed on a semiconductor surface so that it is difficult to control the interface between the ferroelectric and semiconductor (ferroelectric/semiconductor interface). Therefore, it has been said that it is difficult to manufacture a good memory using this MFSFET. For this reason, at present, the main tendency is the memory structure in which a buffer layer is formed on the ferroelectric/semiconductor interface. However, we have proposed an FET of a MFMIS structure, as seen from an equivalent circuit diagram of
FIG. 6 and a
sectional view of
FIG. 7
, in which a buffer layer composed of a metallic layer (M) and an insulating layer (I) is formed on the ferroelectric/semiconductor interface. This FET having MFMIS structure has a gate oxide film
5
, floating gate
6
, ferroelectric film
7
and control gate
8
which are successively stacked on a channel region formed between source/drain regions
2
and
3
of a semiconductor substrate
1
.
In this configuration, when a positive voltage is applied to the control gate
8
over the substrate
1
, the ferroelectric film
7
generates inverted polarization. Even when the application of the voltage to the control gate
8
is ceased, a negative charge is generated on the channel region CH owing to the residual polarization of the ferroelectric film
7
. This state is referred to as the state of “1”.
Reverse to the above case, when a negative voltage is applied to the control gate
8
, the ferroelectric film
8
generates the inverted polarization in an opposite direction that in the above case. Even when the application of the voltage to the control gate
8
, a positive charge is generated to the channel region CH owing to the residual polarization of the ferroelectric film
7
. This state is referred to as the state of “0”. In this way, the information of “1” or “0” can be written in the FET.
The read of the written information is executed by applying a read voltage V
r
to the control gate
8
. The read voltage V
r
is prescribed between the threshold value V
th1
in the state of “1” and the threshold value V
th0
in the state of “0”. It can be decided whether the written information is “1” or “0” by detecting whether or not the drain current has flowed when the read voltage Vr is applied to the control gate
8
.
In this way, the FET of the MIS structure permits a single memory cell to be formed by a single element so that non-destructive read can be made satisfactorily. The former ferroelectric memory including a select transistor and a ferroelectric capacitor, as seen from an equivalent circuit diagram of
FIG. 8 and a
sectional view of
FIG. 9
, can hold charges of two values of “0” and “1” in a single ferroelectric capacitor. For example, as understood from the hysteresis characteristic as shown in
FIG. 10
, where the storage information of “0” is written, with the voltage applied to the capacitor being minus (with a select transistor T
SW
being on, a minus potential is applied to a bit line BL and a plus potential is applied to a plate line PL) after having passed point d, the applied voltage is restored to zero. In this case, the polarized value results in a residual polarized point a so that the storage information of “0” can be written. On the other hand, where storage information of “1” is written, with the voltage applied to the capacitor being plus, after having passed point b, the applied voltage is restored to zero. In this case, the polarized value results in a residual polarized point c so that the storage information of “1” can be written.
The read of data can be carried out in such a manner that the quantity of charges flowing into the bit line when the voltage is applied to the capacitor is detected.
The charges flowing from the ferroelectric capacitor into the bit line changes the potential on the bit line. The bit line has a parasitic bit line capacitance Cb generated because of the presence of the bit line itself. When the select transistor is turned on to select the memory to be read, according to the information stored in each selected memory cell, the charge is outputted onto the bit line. The value obtained when this charge is divided by the entire capacitance of the bit line represents the potential on the bit line.
A difference between the bit line potentials is read in comparison with a predetermined reference potential.
SUMMARY OF THE INVENTION
These memory structures can only execute the write or read of binary information. In order to obviate such inconvenience, an object of the present is to provide a memory structure which can execute the write and read of multilevel information.
In order to attain the above object, in accordance with the invention, there is provided a non-volatile memory comprising:
a ferroelectric transistor including a gate electrode stacked through at least a first ferroelectric layer on the surface of a semiconductor substrate between source/drain regions formed therein; and
a ferroelectric capacitor including a first and a second electrode and a second ferroelectric layer sandwiched between the first and the second electrode, the first electrode being connected to one of the source/drain regions, characterized in that a first potential difference is generated between the gate electrode and the semiconductor substrate to invert the polarization of the first ferroelectric layer, and a second potential difference is generated between the first and the second electrode to invert the polarization of the second ferroelectric layer so that write and read of data of multilevel values are executed.
Preferably the ferroelectric transistor is a transistor of an MFIS structure which is provided with the gate electrode formed through the first ferroelectric layer and a gate insulating film on the surface of the semiconductor substrate between source/drain regions formed therein.
Preferably, the ferroelectric transistor is a transistor of an MFIS structure having a floating gate, the first ferroelectric layer and a control gate stacked through a gate insulating film on the surface of the semiconductor substrate between source/drain regions formed therein.
In this configuration, by combining a voltage applied between the substrate and a gate (word line) such as a control gate and the value of a drain current (channel resistance) under a gate potential of the ferroelectric transistor, the write and read of data of multilevel values can be made very easily.
Prefarably, the first and the second ferroelectric layer are a ferroelectric layer formed in the same step.
In this configuration, in addition to the above effect, a non-volatile memory which can be easily manufactured and a simple structure and great reliability.
Incidentally, where the first and the second ferroelectric layer are formed in the same step, the memory composed of a single transistor and a single capacitor is preferably made of PZT or SBT, but not preferably made of STN.
On the other hand, where the first and the second ferroelectric layer are formed in
Morgan & Lewis & Bockius, LLP
Rohm & Co., Ltd.
Zarabian A.
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