Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2005-09-27
2005-09-27
Lee, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S185050, C365S185110
Reexamination Certificate
active
06950356
ABSTRACT:
The invention relates to a non-volatile memory test structure, comprising a plurality of memory cells arranged in rows and columns, each memory cell comprising at least a memory transistor and having a source terminal, a gate terminal and a drain terminal. In order to provide a fast and effective test structure to be used for fast reliability evaluation in monitoring of non-volatile memory elements on every wafer it is proposed according to the present invention that:—a group of said memory cells is connected in parallel,—the source terminals of the memory cells in the group are connected together and to a source line,—the drain terminals of the memory cells in the group are connected together and to a drain line,—the gate terminals of the memory cells in the group are connected together and to a gate line, and—said gate line has two connections to apply an electrical current to said gate line for using it as a heating means.
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patent: 6320201 (2001-11-01), Corbett et al.
patent: 6747471 (2004-06-01), Chen et al.
patent: 6791171 (2004-09-01), Mok et al.
Lee Vu A.
Zawilski Peter
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