Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-06-15
2001-06-05
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S185290, C365S201000
Reexamination Certificate
active
06243839
ABSTRACT:
TECHNICAL FIELD
The present invention relates to non-volatile memory systems, and more specifically, to a memory system which includes apparatus for testing the memory cells of such systems by automatically writing a data pattern to each memory cell and verifying successful completion of the write operation.
BACKGROUND OF THE INVENTION
In early integrated circuit memory systems, the detailed operation of the memory system was controlled directly by a processor unit which utilized the memory. This was referred to as external control of the memory system operations because the control means was external to the memory itself. Since the operation of many memory systems requires a substantial amount of processor overhead, and since different manufacturers require different operations for optimizing their particular memories, many such systems now include an internal state machine (ISM) for controlling the operation of the memory system. The internal state machine controls the execution of the primary operations of the memory system, including reading, programming and erasing of the memory cells. Each of these primary operations is comprised of a large number of sub-operations which are necessary to carry out the primary operations, with these sub-operations also being controlled by the state machine.
FIG. 1
is a functional block diagram of a conventional non-volatile memory system
1
. The core of memory system
1
is an array
12
of memory cells. The individual cells in array
12
(not shown) are arranged in rows and columns, with there being, for example, a total of 256K eight bit words stored in array
12
. The individual memory cells are accessed by using an eighteen bit address A
0
-A
17
, which is input by means of address pins
13
. Nine of the eighteen address bits are used by X decoder
14
to select the row of array
12
in which a desired memory cell is located and the remaining nine bits are used by Y decoder
16
to select the column of array
12
in which the desired cell is located. Sense amplifiers
50
are used to read the data contained in a memory cell during a read operation or during a data verification step in which the state of a cell is determined after a programming, pre-programming, or erase operation. The sense amplifier circuitry can be combined with the data compare and verify circuits used to compare the state of a cell to a desired state or to the input data used in programming the cell.
Programming or erasing of the memory cells in array
12
is carried out by applying the appropriate voltages to the source, drain, and control gate of a cell for an appropriate time period. This causes electrons to tunnel or be injected from a channel region to a floating gate. The amount of charge residing on the floating gate determines the voltage required on the control gate in order to cause the device to conduct current between the source and drain regions. This is termed the threshold voltage, V
th
, of the cell. Conduction represents an “on” or erased state of the device and corresponds to a logic value of one. An “off” or programmed state is one in which current is not conducted between the source and drain regions and corresponds to a logic value of zero. By setting the threshold voltage of the cell to an appropriate value, the cell can be made to either conduct or not conduct current for a given set of applied voltages. Thus, by determining whether a cell conducts current at a given set of applied voltages, the state of the cell (programmed or erased) can be found.
Memory system
1
contains internal state machine (ISM)
20
which controls the data processing operations and sub-operations performed on memory array
12
. These include the steps necessary for carrying out programming, reading and erasing operations on the memory cells of array
12
. In addition, internal state machine
20
controls operations such as reading or clearing status register
26
, identifying memory system
1
in response to an identification command, and suspending an erase operation. State machine
20
functions to reduce the overhead required of an external processor (not depicted) typically used in conjunction with memory system
1
.
For example, if memory cell array
12
is to be erased (typically, all or large blocks of cells are erased at the same time), the external processor causes the output enable pin {overscore (OE)} to be inactive (high), and the chip enable {overscore (CE)} and write enable {overscore (WE)} pins to be active (low). The processor then issues an 8 bit command
20
H (0010 0000) on data I/O pins
15
(DQ
0
-DQ
7
), typically called an Erase Setup command. This is followed by the issuance of a second eight bit command D
0
H (1101 0000), typically called an Erase Confirm command. Two separate commands are used to initiate the erase operation in order to minimize the possibility of inadvertently beginning an erase procedure.
The commands issued on I/O pins
15
are transferred to data input buffer
22
and then to command execution logic unit
24
. Command execution logic unit
24
receives and interprets the commands used to instruct state machine
20
to initiate and control the steps required for erasing array
12
or carrying out another desired operation. If a programming operation is being executed, the data to be programmed into the memory cells is input using I/O pins
15
, transferred to input buffer
22
, and then placed in input data latch
30
. The data in latch
30
is then made available to sense amplifier circuitry
50
for the cell programming and data verification operations. Once a desired operation sequence is completed, state machine
20
updates 8 bit status register
26
. The contents of status register
26
is transferred to data output buffer
28
, which makes the contents available on data I/O pins
15
of memory system
1
. Status register
26
permits the external processor to monitor certain aspects of the status of state machine
20
during memory array write and erase operations. The external processor periodically polls data I/O pins
15
to read the contents of status register
26
in order to determine whether an erase sequence (or other operation) has been completed and whether the operation was successful.
Memory system
1
verifies the status of the memory cells after performing programming or erasing operations on the cells. Verification occurs by accessing each memory element and evaluating the margins (the voltage differential between the threshold voltage of the memory cells and ground level) that the element has after the operation. The system then decides whether the element needs to be reprogrammed or erased further to achieve a desired operational margin.
The memory array needs to be programmed first in a pre-programming cycle before it can be erased. This is to avoid over-erasing the bits in some memory elements to a negative threshold voltage, thereby rendering the memory inoperative. During this cycle of pre-programming, the memory system needs to check to see if the bits are programmed to a sufficient threshold voltage level. This is accomplished by a pre-programming verification cycle that uses a different evaluation procedure than a regular read operation would use. After successful completion of the pre-programming cycle, a high voltage erase operation is executed. After the erase operation is completed, some memory systems go through an operation to tighten the distribution (reduce the variance) of memory element threshold voltages. This makes the manufacturing process easier and more reproducible. After this procedure, the memory system may perform a re-verify operation to determine if the data in the memory array has remained undisturbed.
FIG. 2
is a state diagram showing the process flow (sub-operations) of a memory system of the type shown in
FIG. 1
during the pre-programming, high voltage erase, and distribution adjustment cycles of a complete erase operation. The complete erase operation starts with a pre-program cycle
200
. This sub-operation programs all the elements in the memory array to a
Micro)n Technology, Inc.
Moise Emmanuel L.
Schwegman Lundberg Woessner & Kluth P.A.
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