Non-volatile memory refresh control circuit

Details Non-volatile memory refresh control circuit Non-volatile memory refresh control circuit

1978-10-03

1980-08-19

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

365228, G11C 700

Patent

active

042187648

ABSTRACT:
A non-volatile memory control circuit for reprogramming non-volatile memory devices before their natural decay causes their "1" and "0" levels to become indistinguishable. Signals representing the memory states of the non-volatile memory devices are temporarily stored while the non-volatile memory devices are erased. After erasure the memory states are rewritten into the non-volatile memory devices. After rewriting, the control circuit is automatically reset. The erase/write operation is triggered by interrogating a second set of "parallel" non-volatile memory devices containing a predetermined data pattern, the interrogation occurring with a threshold detection level greater than that at which the memory levels of the primary non-volatile devices become indistinguishable.

REFERENCES:
patent: 3761901 (1973-09-01), Aneshansley
patent: 3771148 (1973-11-01), Aneshansley
patent: 3796998 (1974-03-01), Appelt
Johnson, Self-Actuating Refresh Scheme for Dynamic Memories, IBM Tech. Disc. Bul., vol. 20, No. 11A, 4/78, pp. 4399-4400.
Shattuck et al., Memory Protection System, IBM Tech. Disc. Bul., vol. 9, No. 6, 11/66, pp. 731-734.

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