Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-01-30
2007-01-30
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S316000, C257S320000, C257S321000, C257S322000, C257S324000, C257S411000, C257S412000
Reexamination Certificate
active
11160741
ABSTRACT:
A method of fabrication a non-volatile memory is provided. A stacked structure is formed on a substrate, the stacked structure including a gate dielectric layer and a control gate. Then, a first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed on the top and sidewalls of the stacked structure and the exposed substrate. Thereafter, a pair of charge storage layers are formed over the substrate to respectively cover a portion of the top and sidewalls of the stacked structure, and a gap exists between each of the charge storage layers.
REFERENCES:
patent: 5625213 (1997-04-01), Hong et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 2004/0256657 (2004-12-01), Hung et al.
Article titled “A Novel CMOS-Compatible Top-Floating-Gate EEPROM Cell for Embedded Applications” jointly published by Mc Carthy et al. on Jul. 2003 (4 pages).
Article titled “90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F2/bit and programming throughput of 10MB/s” jointly published by Sasago et al. in 2003 (4 pages).
Jiang Chyun IP Office
MACRONIX International Co. Ltd.
Wojciechowicz Edward
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