Non-volatile memory erase circuitry

Details Non-volatile memory erase circuitry Non-volatile memory erase circuitry

2006-06-06

2006-06-06

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S185180, C365S185190, C365S236000

Reexamination Certificate

active

07057945

ABSTRACT:
A non-volatile memory device includes floating gate memory cells, a pulse counter and voltage pump control circuitry. The control circuitry selectively activates pumps in response to a count output of the counter. In one embodiment, the pump output current is increased as the counter output increases. The memory allows for erase operations that reduce leakage current during initiation of an erase operation.

REFERENCES:
patent: 4752699 (1988-06-01), Cranford, Jr. et al.
patent: 5463588 (1995-10-01), Chonan
patent: 5801987 (1998-09-01), Dinh
patent: 6278639 (2001-08-01), Hosono et al.
patent: 6279070 (2001-08-01), Jeong et al.
patent: 6320796 (2001-11-01), Voo et al.
patent: 6385093 (2002-05-01), Bautista, Jr. et al.
patent: 6421757 (2002-07-01), Wang et al.
patent: 6643181 (2003-11-01), Sofer et al.

Affiliated with

Also associated with

Rating

Non-volatile memory erase circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-volatile memory erase circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile memory erase circuitry will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3629730