Non-volatile memory devices including local control gates on...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S185110, C365S185130, C365S185170, C365S185180, C365S185270, C365S185290, C365S185330

Reexamination Certificate

active

07733696

ABSTRACT:
A non-volatile integrated circuit memory device may include a semiconductor substrate having first and second electrically isolated wells of a same conductivity type. A first plurality of non-volatile memory cell transistors may be provided on the first well, and a second plurality of non-volatile memory cell transistors may be provided on the second well. A local control gate line may be electrically coupled with the first and second pluralities of non-volatile memory cell transistors, and a group selection transistor may be electrically coupled between the local control gate line and a global control gate line. More particularly, the group selection transistor may be configured to electrically couple and decouple the local control gate line and the global control gate line responsive to a group selection gate signal applied to a gate of the group selection transistor. Related methods and systems are also discussed.

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English translation of Notice of Allowance for Korean Application No. 10-2006-0095901; Aug. 21, 2007.
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