Non-volatile memory device with row redundancy

Details Non-volatile memory device with row redundancy Non-volatile memory device with row redundancy

2000-05-12

2001-10-09

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S200000, C365S185110, C365S185130, C365S230060

Reexamination Certificate

active

06301152

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention refers to a non-volatile memory device. In particular the aforementioned in vention refers to a non-volatile memory device with row redunddancy.
BACKGROUND OF THE INVENTION
In a non-volatile semiconductor memory device (EPROM or Flash) it is necessary that the matrix of memory cells contained therein has all the cells perfectly working during the various operation stages of the device (reading, programming, erasing). In fact, the presence of only one non working cell (bit-fail) is sufficient for the entire memory device to become useless. Such failure of the memory cell is ascribable, for example, to causes deriving from the technological process, such as the existence of conductive layers short-circuiting with each other, the variation of some process parameters, and the failure of the dielectric layers. It is therefore necessary to avail of adequate expedients within the memory device that allow one to detect and to correct bit-fails, and therefore to increase the production yield of the memory devices. To this purpose, circuit solutions for the correction and the recognition of bit-fail are utilized. A traditionally utilized technique consists in the use of memory cells in addition to the ones constituting the memory matrix that are purposed to substitute the damaged memory cells. Such memory cells, named redundancy cells, are opportunely controlled by circuits additional to the ones that are already present within the device. In particular, in view of the organization of the memory it is necessary to use entire rows or entire columns made up of redundancy memory cells that substitute corresponding rows or columns of the matrix even in the presence of a single bit-fail located in them. In this way it is necessary to make a compromise between the failure correcting capacity and the area required for the redundancy handling circuits.
The choice of the type of organization of the redundancy cells to be utilized in the memory device (row redundancy, column redundancy, or both) is essentially tied to the knowledge of the distribution and of the typology of the defects present in the matrix for a fixed integration technology process.
FIG. 1
shows the simplified architecture of a flash type non-volatile memory utilizing the row redundancy technique. The architecture includes a cell matrix
1
orderly organized into rows and columns, a row decoder block
2
purposed to decode the row addresses, a column decoder block
3
purposed to decode the column addresses, a reading block containing the reading circuits (sense amplifiers)
4
, and an output buffer
5
. For exemplifying but not limiting purpose an architecture with a single redundancy sector
7
for the correction of bit-fails equally probably distributed in all the matrix sectors has been assumed. In a flash memory the cell matrix is divided into different units or sectors having prefixed capacity. The selective access to the sectors is obtained by providing an organization of the sectors by rows or by columns, as well as a physical separation of the source lines of each sector. In the first case the columns are shared among all sectors and the selection of the sector is made by using the row address, while in the second case the rows are shared among the sectors and the selection is made on the column address. In addition, it is possible to realize a hierarchic row (column) organization that consists in the realization of global rows (columns), that means that they are shared among all sectors, to which the local lines (columns) of the single sectors are connected which are enabled only for the sector being selected.
The detection of the defective cells takes place during the testing stage of the device. In the presence of defective cells, an onchip control circuitry allows the substitution of the entire matrix row with a redundant row, in such a way that the access to the latter is completely transparent for the final user. This operation consists in the permanent memorization of the address of the defective row by means of non-volatile memory cells named UPROM (Unerasable Programmable ROM)
10
. The UPROM cells referring to a redundant row are organized in a register suitable to permanently contain the address that was set during the testing stage. In this way, at each access to the memory, the row address being selected must be compared with the content of the redundancy registers. Each register memorizes a row address and allows the selection of the corresponding redundant row before carrying out a reading, programming or erasing operation.
In order to ensure the maximum corrective power for a prefixed number of rows per sector, that is the maximum number of retrievable bit-fails in a sector by substitution of the corresponding row, it should be necessary to fix a number of redundancy rows equal to the number of rows in the sector (one to one correspondence). In practice, this choice turns out to be disadvantageous because of the area required by the redundancy management circuits, therefore the number of redundancy rows is fixed at a value lower than the one of the sector rows since a compromise is made between a the corrective power and the area occupied on silicon. In this way a redundant row can substitute only a prefixed row within the set of a prefixed number of sector rows (therefore with a many-to-one correspondence between the rows in a sector and the redundancy row). This choice allows in any case the correction of a bit-fail equally distributed on all sectors of the matrix.
With the architecture of the known art, the redundancy rows are pre-decoded by the same row decoding signals of the matrix sectors. The row decoding takes up a sufficient number of bits of the row address for the generation of Nm signals of row selection (P
0
, P
1
. . . PNm−1). In the architecture of the row decoding with the known art, the aforementioned decoding signals enable an equal number of selection transistors (typically N-channel MOS transistors) for the connection of the row to the predecoding logic located downstream. In an analogous way the redundancy rows are selected by Nr signals PR
0
, PR
1
. . . PRNr−1. Two cases can occur, that are reported in
FIGS. 2 and 3
, where a hierarchic row decoding has been assumed.
If Nm>Nr, each redundancy row of the sector
210
is shared by groups
10
with Nm/Nr rows of the matrix sectors
200
and the selection signal of the redundancy row is activated only if at least one row of the group
10
is activated, therefore, for example, PR
0
=P
0
or P
1
or P
2
. . . or P(Nm/Nr−1) (FIG.
2
).
If Nm=Nr, a single row of the matrix sector
200
is associated with each redundancy row of the sector
210
, as they are both decoded by the same signal, therefore, for example, PR
0
=P
0
(FIG.
3
). Such solution allows the maximum corrective power.
In a Flash memory architecture utilizing the row redundancy technique, according to the solution of the known art, the redundancy cells and the matrix ones share the same bit-lines. Said redundancy cells can be realized in a dedicated sector or distributed inside each matrix sector. In addition the redundancy cells share the source line that must be in turn electrically shared with the one of the matrix rows with which they will be associated. This condition is essential since the architecture of a Flash memory imposes that the redundancy cells must be erased simultaneously with the ones of the sector they are referred to.
The access time of a memory word in an architecture utilizing the row redundancy technique turns out to be greater than the one obtainable with memory architectures that do not use this technique. This access time depends, for example, on the delays of propagation of the signals along the interconnection lines caused by the non-ideal effects due to their physical realization, and on the time required to carry out the comparison between row addresses and the subsequent selection of the redundant row.
FIG. 4
shows the time diagram of an access

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