Non-volatile memory device with enlarged trapping layer

Details Non-volatile memory device with enlarged trapping layer Non-volatile memory device with enlarged trapping layer

2006-04-11

2006-04-11

Lee, Hsien-Ming (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S324000, C438S261000

Reexamination Certificate

active

07026682

ABSTRACT:
Methods for making a nonvolatile memory device, such as an NROM device that has an oxide-nitride-oxide layer beneath at least one word line structure, are disclosed. The oxide-nitride-oxide layer is in the form of a plurality of oxide-nitride block structures disposed over an oxide layer, with each of the oxide-nitride block structures overlapping two adjoining bit lines. A dielectric resolution enhancement coating technique is performed to precisely control the oxide-nitride block structure dimensions.

REFERENCES:
patent: 6366501 (2002-04-01), Thurgate et al.
patent: 6448606 (2002-09-01), Yu et al.

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