Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-05
2003-11-18
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000
Reexamination Certificate
active
06649967
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile memory device, more particularly to a non-volatile memory device having a short erasing time and high reliability, and a fabrication method of the same.
2. Discussion of the Related Art
Generally, a non-volatile memory device is a memory device whose threshold voltage is changed according to the charging or discharging of a floating gate that is electrically insulated.
A programming operation of a conventional non-volatile memory device is performed by a channel hot electron (CHE) method in which hot electrons generated in a drain region when the device is operated in its saturation state are injected into the floating gate through a gate oxide film. An erasing operation is performed by emitting electrons from a floating gate into a channel or a gate oxide film of an overlapped region between a source and the floating gate. In order to perform the erasing operation by using the gate oxide film, the gate oxide film has to be very thin (less than 100 Å), yet it is very difficult to obtain a highly reliable fabrication of thin gate oxide film.
To improve the reliability of the gate oxide film, a method for emitting charges of the floating gate by using an additional erasing gate has been introduced. In most conventional devices using the additional erasing gate, since polysilicon is used for an oxide film of the floating gate, the oxide film of the floating gate is thicker than the gate oxide film of the channel region and the fabrication process thereof is relatively easy. However, the erasing method using the erasing gate requires a high voltage because of the thick oxide film of the floating gate. Furthermore, in a read operation, electrons are undesirably injected into the floating gate from the erasing gate, causing a threshold voltage of the device to be undesirably changed.
FIG. 1
a
is a cross sectional view showing a structure of a simple stacked non-volatile memory device of the conventional art, and
FIG. 1
b
is a symbolic structure of the non-volatile memory device cell of the conventional art.
Referring to
FIG. 1
a
, a tunneling insulation film
2
is formed on a p-type semiconductor substrate
1
and a floating gate
3
is formed on the tunneling insulation film
2
. A dielectric layer
4
is formed on the floating gate
3
and a control gate
5
is formed on the dielectric layer
4
. In surfaces of the p-type substrate
1
at both sides of the floating gate
3
, n-type source region
6
a
and n-type drain region
6
b
are formed, respectively.
An effective cell size of a simple stack non-volatile memory device having a structure of
FIG. 1
a
is small, but a coupling constant of the control gate
5
also becomes undesirably small. Furthermore, a serious problem is that the coupling constant becomes smaller as the effective cell size becomes smaller. Therefore, in order to prevent the coupling constant from becoming smaller, several attempts of forming an O—N—O (oxide-nitride-oxide) film as the dielectric film
4
between the floating gate
3
and the control gate
5
have been made, but the overall process for forming the O—N—O film is complex and a high annealing process is required.
As shown in
FIG. 1
a
and
FIG. 1
b
, a non-volatile memory cell includes a floating gate
3
, a control gate
5
for controlling the amount of charges supplied to the floating gate
3
for programming (e.g., data write) operation, and a field effect transistor is used for reading (or verifying) the amount of charges carrier provided to the floating gate
3
during the programming operation. The field effect transistor includes the floating gate
3
, the source
6
a
, the drain
6
b
, and channel
7
between the drain
6
b
and the source
6
a.
The conventional art non-volatile memory cell constructed as described above is operated by the current between the drain
6
b
and the source
6
a
when the control gate
5
and the drain
6
b
are driven by voltages that are high enough to guarantee the operation of the cell. At this time, the current between the drain
6
b
and the source
6
a
is compared with a reference current. If the current is equal to or less than the reference current, a programming completion signal is generated. A conventional non-volatile memory device and the fabrication method of the same will be explained as follows.
FIG. 2
is a cross sectional view showing the structure of a conventional non-volatile memory device. As shown in
FIG. 2
, the conventional non-volatile memory device comprises a first floating gate
13
formed on an insulation film
12
which is formed on a predetermined portion of a p-type semiconductor substrate
11
; a first insulation film
14
formed on an entire surface of the substrate
11
including the first floating gate
13
, with a contact hole to expose a predetermined portion of the first floating gate
13
; a second floating gate
16
a
formed in the contact hole and on the first insulation film
14
adjacent to the contact hole; a second insulation film
17
, a control gate
18
a
and a cap insulator
19
being sequentially stacked so as to have an alignment with one side of the second floating gate
16
a
and exposed surface of the other side of the second floating gate
16
a
; a third insulation film sidewall
21
formed at both sides of the cap insulator
19
, the control gate
18
a
and the second insulation film
17
; a tunneling insulation film
22
formed on the exposed surface of the second floating gate
16
a
; and an erasing gate
23
formed adjacent to the tunneling insulation film
22
.
FIG. 3
a
to
FIG. 3
g
are cross sectional views showing the fabrication process for the conventional non-volatile memory device.
As shown in
FIG. 3
a
, a gate insulation film
12
is formed on a p-type semiconductor substrate
11
. A first polysilicon layer for a floating gate is formed on the gate insulation film
12
. By selectively removing the first polysilicon layer by a photolithography process, the first floating gate
13
having a predetermined size is formed. The first floating gate
13
is formed as an island shape by patterning the first polysilicon layer in a column direction by the photolithography process and then patterning the patterned polysilicon layer in the direction perpendicular to the column direction by photolithography process. At both sides of the first floating gate
13
, insulation sidewalls (not shown in
FIG. 3
a
) are formed and electrically insulate the first floating gate
13
. Impurity ions of different conductivity type from the semiconductor substrate
11
are injected into the surface regions of the semiconductor substrate
11
at both sides of the first floating gate
13
. These regions are used as a source region and a drain region (not shown in
FIG. 3
a
), respectively.
As shown in
FIG. 3
b
, on the entire surface of the semiconductor substrate
11
including the first floating gate
13
, a first insulation film
14
composed of oxide film, nitride film/oxide film using low pressure chemical vapor deposition (LPCVD), or their combination is formed. A contact hole
15
is formed by selectively removing a portion of the first insulation film
14
by a photolithography process so that a predetermined portion of the top surface of the first floating gate
13
is exposed.
As shown in
FIG. 3
c
, a second polysilicon layer
16
for a second floating gate is formed over the entire surface of the semiconductor substrate
11
including the contact hole
15
. In this case, in order to form the second polysilicon layer
16
, a doped polysilicon layer may be used or an undoped polysilicon layer may be deposited first and then doped by ion injection method or diffusion source doping method.
Over the entire surface of the semiconductor substrate
11
including the second polysilicon layer
16
, a second insulation film
17
of 100~500 Å thickness composed of a silicon oxide film or a combination of LPCVD oxide film and silicon nitride film is formed. Subsequently, a third polysilicon layer
Kwon Wook Hyun
Na Kee Yeol
Hyundai Electronics Industries Co,. Ltd.
Loke Steven
Owens Douglas W.
LandOfFree
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