Non-volatile memory device having select transistor...

Details Non-volatile memory device having select transistor... Non-volatile memory device having select transistor...

2003-07-14

2004-09-21

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S239000, C257S261000, C257S316000, C257S318000, C257S322000, C438S201000, C438S211000, C438S241000, C438S257000, C438S261000, C438S266000

Reexamination Certificate

active

06794711

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority from Korean Patent Application No. 2002-55003, filed Sep. 11, 2002, in the Korean Intellectual Property Office, the contents of which are hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention This disclosure relates to a non-volatile memory device and a method for fabricating the device, and more particularly, to a non-volatile memory device having a select transistor structure and silicon-oxide-nitride-oxide-silicon (SONOS) cell structure and a method for fabricating the device.
2. Description of the Related Art
In general, semiconductor memory devices used for storing data can be divided into volatile devices and non-volatile devices. Volatile memory devices lose data stored therein when a supply voltage is interrupted, while non-volatile memory devices retain the data stored therein even if the supply voltage is interrupted. Accordingly, non-volatile memory devices are widely used when the supply voltage is not always applied or often interrupted, or when a device requires only a low voltage, such as a mobile telephone, a memory card for storing music and/or image data, and other application devices.
In general, cell transistors of the non-volatile memory device have a stacked gate structure. The stacked gate structure includes a gate insulating layer which is sequentially stacked on a channel region of the cell transistor, a floating gate electrode, an insulating layer between gates, and a control gate electrode. The non-volatile memory device often can be formed of a silicon layer in which a channel region is formed, an oxide layer which forms a tunneling layer, a nitride layer which is used as a charge trapping layer, an oxide layer which is used as a blocking layer, and a silicon layer which is used as a control gate electrode. This structure is often referred to as a silicon-oxide-nitride-oxide-silicon (or SONOS) cell structure.
FIG. 1
is a sectional diagram of a non-volatile memory device having a general SONOS cell structure.
With reference to
FIG. 1
, an oxide-nitride-oxide (ONO) layer
110
is formed on a silicon substrate
102
where a source region
104
and a drain region
106
are separated from each other by a predetermined distance. The ONO layer
110
has a stacked structure, which is formed such that a tunneling layer
112
formed of a first silicon oxide layer, a charge trapping layer
114
formed of a silicon nitride layer, and a blocking layer
116
formed of a second silicon oxide layer are sequentially stacked on a surface of the silicon substrate
102
. A control gate electrode
120
, which is formed of a polysilicon layer, is formed on the ONO layer
110
.
In the non-volatile memory device, to perform a programming or writing operation, a positive bias voltage is applied to the control gate electrode
120
and the drain region
106
, and the source region
104
is grounded. The voltage that is applied to the control gate electrode
120
and the drain region
106
induces a vertical electric field and a horizontal electric field along the channel region from the source region
104
to the drain region
106
. Due to the electric fields, electrons are pushed away from the source region
104
and accelerate towards the drain region
106
. The electrons gain energy from moving along the channel region, and some electrons enter into a hot state where they can gain enough energy to enter the charge trapping layer
114
, leaping over the potential barrier of the tunneling layer
112
. This happens most frequently near the drain region
106
, because the electrons can gain the greatest amount of energy in that region. Once the electrons in the hot state enter the charge trapping layer
114
, the electrons in the hot state are trapped in the charge trapping layer
114
and become stored therein, and thus the threshold voltage of the memory cell increases.
In the non-volatile memory device, to perform an erasing operation, a different voltage from the voltage used in programming or reading the memory cell is required. For example, a positive bias voltage is applied to the drain region
106
, and a negative bias voltage is applied to the control gate electrode
120
. Then, the source region
104
is floated. Thus, the electrons, which are stored in the charge trapping layer
114
, move towards the drain region
106
, and holes within the drain region
106
migrate to the charge trapping layer
114
. Therefore, the electrons stored in the charge trapping layer
114
are removed or neutralized by the holes, and thus data on the memory cell is erased.
However, the non-volatile memory device having the above-mentioned structure cannot control a current in the channel region when the programming operation is performed in byte mode. That is, the programming operation must be performed in bit mode, and a certain amount of power is continuously wasted because the current in the channel region cannot be controlled when the operation is executed.
Embodiments of the invention address this and other limitation in the product.
SUMMARY OF THE INVENTION
Embodiments of the invention provide a non-volatile memory device having a select transistor structure and a SONOS cell structure which make it possible to perform programming operation in byte mode and to control a current in a channel region when the programming operation is executed. Also provided is a method for manufacturing the non-volatile memory device.


REFERENCES:
patent: 5559735 (1996-09-01), Ono et al.
patent: 5780893 (1998-07-01), Sugaya

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