Non-volatile memory device for reducing layout area of...

Details Non-volatile memory device for reducing layout area of... Non-volatile memory device for reducing layout area of...

2011-04-26

2011-04-26

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185110, C365S185130, C365S185230, C365S185240, C365S185170

Reexamination Certificate

active

07933154

ABSTRACT:
A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to 3, to a corresponding wordline of the plurality of wordlines in a program mode, and a second type global wordline decoder configured to selectively apply (n−1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder.

REFERENCES:
patent: 6865114 (2005-03-01), Pio
patent: 7151686 (2006-12-01), Sugimae et al.
patent: 2004/0080980 (2004-04-01), Lee
patent: 2005/0180213 (2005-08-01), Abe et al.
patent: 2007/0171719 (2007-07-01), Hemink et al.
patent: 10-2007-0018216 (2007-02-01), None

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