Non-volatile memory device and system having reduced bit...

Details Non-volatile memory device and system having reduced bit... Non-volatile memory device and system having reduced bit...

2010-02-01

2011-11-01

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S203000

Reexamination Certificate

active

08050104

ABSTRACT:
A non-volatile memory device and system are provided. The non-volatile memory device including; a memory cell array of memory blocks, and a bit line bias block connected to the bit lines and configured to precharge the bit lines, a page buffer precharging the plurality of bit lines and sensing data stored in the memory block via the bit lines, and a controller controlling the bit line bias block to simultaneously precharge the bit lines with the page buffer, thereby reducing the bit line bias time.

REFERENCES:
patent: 5768215 (1998-06-01), Kwon et al.
patent: 5790466 (1998-08-01), Hotta
patent: 6490199 (2002-12-01), Lee et al.
patent: 2003/0112673 (2003-06-01), Takano et al.
patent: 2007/0121376 (2007-05-01), Toda
patent: 2007/0165473 (2007-07-01), Suzuki et al.
patent: 09147580 (1997-06-01), None
patent: 2002237194 (2002-08-01), None
patent: 100245244 (2000-03-01), None
patent: 1020020064576 (2002-08-01), None
patent: 1020050064666 (2005-06-01), None

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