Non-volatile memory device and page buffer circuit thereof

Details Non-volatile memory device and page buffer circuit thereof Non-volatile memory device and page buffer circuit thereof

2009-07-27

2011-11-08

Tran, Michael (Department: 2827)

Static information storage and retrieval

Floating gate

Multiple values

C365S185240

Reexamination Certificate

active

08054682

ABSTRACT:
A non-volatile memory device includes a cell array including a plurality of memory cells, a page buffer block controlling bitlines of the plurality of memory cells to program the memory cells to a first target state or a second target state, and a control logic configured to skip a verify operation for the memory cells programmed to the first target state and perform a verify operation for the memory cells programmed to the second target state during a second program loop when the memory cells programmed to the first target state are determined to be in a pass condition during a first program loop.

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