Non-volatile memory device and method of operation therefor

Details Non-volatile memory device and method of operation therefor Non-volatile memory device and method of operation therefor

2007-01-17

2010-06-08

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185120, C365S185170, C365S185180, C365S185230, C365S185250, C365S185260, C365S185270, C365S185330

Reexamination Certificate

active

07733695

ABSTRACT:
In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

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European Search Report issued in connection with corresponding European Patent Application No. 07250657.9 mailed on Aug. 10, 2007.

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