Non-volatile memory device and erase method

Details Non-volatile memory device and erase method Non-volatile memory device and erase method

2009-08-12

2011-11-08

Le, Vu (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110

Reexamination Certificate

active

08054688

ABSTRACT:
Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first and second semiconductor substrates, and a plurality of word lines connected to gates of the plurality of non-volatile memory cell transistors. The plurality of non-volatile memory cell transistors are grouped into two or more memory cell blocks, such that a first voltage is applied to the first semiconductor substrate including a first memory cell block to be erased, and either (1) a second voltage less than the first voltage and greater than 0V is applied to the second semiconductor substrate not including the first memory cell block, or (2) the second semiconductor substrate not including the first memory cell block is allowed to electrically float.

REFERENCES:
patent: 7592664 (2009-09-01), Lee
patent: 7728427 (2010-06-01), Gabara
patent: 2002368141 (2002-12-01), None
patent: 1020060098044 (2006-09-01), None
patent: 100673019 (2007-01-01), None

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