Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2007-10-09
2007-10-09
Graham, Kretelia (Department: 2827)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S189110
Reexamination Certificate
active
11215850
ABSTRACT:
During an erase operation, lower decoder groups20(i) and21(i) (i=1 to m) of erase-target sectors are connected, at their respective low voltage power supply terminals (VL), to a first negative voltage supply line (VM) via switches (B) (50and51, respectively) and a negative bias voltage is supplied to local word lines. The first negative voltage supply line (VM) is connected to a level shift circuit (4), and is level-shifted to a voltage at a higher level relative to that of a second negative voltage (VMP) which is output from a negative voltage generator circuit (3) via a second negative voltage supply line (VMP). An upper decoder group (10) is connected, at its low voltage power supply terminal (VL), to the second negative voltage line (VMP) via a switch (A) (5). All global word lines GWL0(i) (i=0 to m) are biased to the second negative voltage (VMP) by an active signal (ACTB0(i)) at high level supplied to the upper decoder group (10) and are biased to a lower voltage level relative to the first negative voltage (VM) as a bias voltage to the local word lines.
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Graham Kretelia
Ingrassia Fisher & Lorenz PC
Spansion LLC
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