Non-volatile memory circuits, architecture

Details Non-volatile memory circuits, architecture Non-volatile memory circuits, architecture

1995-05-09

1996-07-09

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

365 45, G11C 1300

Patent

active

055351670

ABSTRACT:
The invention enables random read and write operations into cells in an array that contains staggered source or drain connections from the memory cells in a given column. The invention comprises only one row decoder providing the required voltages to the read word lines during reading, programming and erase operations. The invention reduces the effective programming time of a single cell and of an entire row of cells that program using hot electrons.
According to another aspect of the invention the asymmetry in programming of split gate EEPROM is used to reverse bias the cell so a plurality of digital bits that were stored by D/A converter in the cell according to a curve are read out by an A/D converter with large voltage difference between logical states.

REFERENCES:
patent: 4318188 (1922-03-01), Hoffmann

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