Non-volatile memory circuit for lengthening service life of non-

Details Non-volatile memory circuit for lengthening service life of non- Non-volatile memory circuit for lengthening service life of non-

1995-01-23

1996-05-07

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Flip-flop

36518905, 365194, 3652335, G11C 700

Patent

active

055153232

ABSTRACT:
A memory cell array is constructed by electrically programmable non-volatile memory cells. A memory peripheral circuit creates an address signal for designating an address in the memory cell array by means of the row decoder and the column decoder to effect the access operation for the memory cell array. An ATD circuit for generating a control signal which permits selection of the memory cell involved in the access operation in the memory cell array for a preset period of time in response to a variation of the address signal is provided. A latch circuit for latching readout data from the memory cell in an active period of the control signal is provided. That is, all of the memory cells in the memory cell array are set in the non-selected state in a period other than the active period of the control signal.

REFERENCES:
patent: 5035284 (1994-04-01), Iwase
patent: 5313434 (1994-05-01), Abe
patent: 5313435 (1994-05-01), Kim et al.
patent: 5343432 (1994-08-01), Matsno et al.
patent: 5404334 (1995-04-01), Pascucci et al.

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