Non-volatile memory cells with selectively formed floating gate

Details Non-volatile memory cells with selectively formed floating gate Non-volatile memory cells with selectively formed floating gate

2003-03-19

2004-08-17

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S321000, C257S327000, C438S257000, C438S296000, C438S593000

Reexamination Certificate

active

06777741

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to semiconductor memories, and is particular to a non-volatile memory and an improved process for manufacturing it.
FIGS. 1A-1B
illustrate a prior art process for forming non-volatile memory cells, such as flash cells, with shallow trench isolation regions separating adjacent cell structures. After depositing an optional pad oxide layer and a nitride layer, an isolation mask
11
is used to define shallow trench isolation regions
12
, which after etching, are filled with material, such as high density plasma (HDP) oxide as shown in
FIGS. 1A-1B
. Subsequently, chemical-mechanical polishing (CMP) is performed followed by removal of the nitride layer.
Well and channel masking, and respective implants are then performed (not shown). Subsequently, tunnel oxide layer
13
is formed in the memory array area, followed by the deposition of a first polysilicon layer (Poly
1
). A separate mask and etch are applied to the device to pattern the polysilicon layer in the memory array to form floating gates
14
. Thus, the formation of shallow trench isolation regions
12
and floating gates
14
are separated in this process.
The formation of floating gates
14
is followed by conventional processing steps, such as the deposition of an insulating dielectric layer of oxide-nitride-oxide (ONO), ONO removal from the peripheral circuit regions, formation of high voltage (HV) and (if separate from the tunnel oxide) low voltage (LV) gate oxide layers for peripheral transistors, the deposition of a second polysilicon layer (Poly
2
), and the patterning the second polysilicon layer to form control gates of the memory cells and gates of transistors in the peripheral regions. Typically this is formed by a self-aligned etch. Subsequently, source/drain junctions of memory cells and periphery transistors are formed, and polysilicon-to-metal dielectric layers are formed (e.g. IPO, PSG, BPSG). The process is completed by back end steps such as forming contacts, metallization, interconnections, and passivation.
The disadvantages of the process of
FIGS. 1A-1B
include the fact that separate masks are required to form shallow trench isolation regions
12
and floating gates
14
, which increases the total number of masking steps. In addition, the spacing between floating gates
14
is determined by limitations of the photolithography process used. Floating gates
14
must be maintained at least a specified minimum distance apart from each other to maintain isolation between the floating gates of adjacent memory cells. Photolithography processes typically cannot resolve features of the transistors below a certain minimum width determined by characteristics of the photolithography equipment and process technology employed.
In memory arrays, cell transistors are separated by isolation regions. The width of isolation regions (ISO space in
FIG. 1B
) is limited by photolithographic resolution of floating gate to floating gate spacing between cells, and the requirements of floating gate to isolation overlap to maintain a desired control-to-floating gate coupling ratio. Depending on the process technology employed, Poly
1
to Poly
1
spacing cannot be typically reduced below the minimum feature size resolution.
For instance, in 0.18 &mgr;m process technology, the minimum spacing between floating gates
14
will be defined at about 0.18 &mgr;m to maintain isolation, which limits memory cell size scaling. Further, although the mask for floating gates
14
is designated as a critical mask with more stringent requirements on misalignment tolerance, Poly
1
mask misalignment may significantly impact memory cell characteristics and prevent the size of the memory cells from being reduced.
FIG. 1B
shows an example of Poly
1
misalignment.
For instance, if the Poly
1
mask is misaligned in such a way that, after patterning, a Poly
1
edge is on the active area instead of the isolation region, or even at the border of the isolation and active regions, the cell transistor and the whole memory array will not function properly. To prevent this, the Poly
1
to ISO (isolation) overlap should be large enough to allow for worst case misalignment. Thus, the Poly
1
to Poly
1
spacing requirements and misalignment considerations limit memory cell, and overall flash chip size.
FIGS. 2A-2D
illustrate another conventional non-volatile memory process. After proper processing and cleaning the silicon substrate (e.g. using sacrificial oxide growth and etch), tunnel oxide layer
20
is formed, followed by deposition of first polysilicon layer
21
(Poly
1
), followed by the formation of an optional pad oxide layer and a nitride layer, as shown in FIG.
2
A. Then, photoresist is deposited and used to pattern for the formation of shallow trench isolation (STI) regions
25
and polysilicon layer
21
as shown in FIG.
2
B. Thus, the Poly
1
patterning in this process is self-aligned to forming isolation regions (i.e., shallow trench isolation regions). Subsequently, trench isolation regions
25
are filled with HDP gap filling material
26
as shown in FIG.
2
C.
Next, the well and channel implantation stepw are performed. After that, a second polysilicon layer
27
is deposited and patterned such that the patterned second polysilicon layer
27
together with the previously patterned first Poly
1
layer
21
form the floating gates for the cells, as shown in FIG.
2
D. Polysilicon layer
27
is also referred to as Poly
1
, because it is in ohmic contact with polysilicon layer
21
. Accordingly, a separate mask is needed for defining the location of second polysilicon layer
27
. The second polysilicon layer
27
serves to provide the floating gate overlap of isolation regions
26
to increase the floating gate-to-control gate coupling ratio. Then, inter-poly dielectric layer
28
(e.g., an ONO composite layer) is deposited. After ONO is removed from the peripheral circuit area of the device and the peripheral transistors' gate oxide has been formed, polysilicon layer
29
(Poly
2
) is deposited and patterned to form the lower layer of the control gate in the memory array, as well as the gates of the peripheral transistors. The memory cell gate stack is then formed by a self-aligned etch. Other conventional steps may follow.
Although the process of
FIGS. 2A-2D
involves forming shallow trench regions
25
to be self-aligned with the first Poly
1
layer
21
, an additional mask is still necessary to pattern the second Poly
1
layer
27
so that the floating gate regions overlap isolation regions
26
, increasing the total masking steps. A further disadvantage is the fact that the spacing between the floating gates in the memory array is determined by limitations of the photolithographic process used for forming the second Poly
1
layer
27
. Furthermore, the mask used to form second Poly
1
layer
27
may be misaligned causing limitations on reducing the memory transistor size, as discussed above.
It would therefore be desirable to provide a process for forming non-volatile memory cells wherein the spacing between floating gates of the cells can be reduced without being limited by a photolithography process. It would be further desirable to minimize or eliminate the problem of floating gate misalignment that also limits cell size reduction.
BRIEF SUMMARY OF THE INVENTION
The present invention provides methods and structures for arrays of non-volatile memory transistors (e.g., flash memory cells) which include floating gates formed from two layers of material such as polysilicon. The second (upper) floating gate layer is selectively grown or deposited on top of the first floating gate layer, eliminating the need to mask the deposition of the second floating gate layer. This allows the memory transistors to be separated by isolation regions which can be more aggressively scaled to smaller dimensions.
In a preferred embodiment, the second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. Be

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