Non-volatile memory cell array for improved data retention...

Details Non-volatile memory cell array for improved data retention... Non-volatile memory cell array for improved data retention...

2007-08-21

2007-08-21

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Simultaneous operations

C365S185290, C365S185140

Reexamination Certificate

active

11258745

ABSTRACT:
A method is provided which includes erasing a first plurality of non-volatile memory bit cells in a memory block comprising a third plurality of memory bit cells during an erase procedure, such that upon completion of the erase procedure, the first plurality of non-volatile memory bit cells are at an erased state. The method also includes programming a second plurality of non-volatile memory bit cells in the memory block during the erase procedure, such that the second plurality of non-volatile memory bit cells is a subset of the third plurality of non-volatile memory bit cells and upon completion of the erase procedure, the second plurality of non-volatile memory bit cells are at a programmed state.

REFERENCES:
patent: 6172910 (2001-01-01), Lee
patent: 6344994 (2002-02-01), Hamilton
patent: 6717848 (2004-04-01), Kim et al.
patent: 2004/0208056 (2004-10-01), Sim

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