Non-volatile memory cell and sensing method

Details Non-volatile memory cell and sensing method Non-volatile memory cell and sensing method

2001-02-21

2002-05-28

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06396730

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a non-volatile memory, and more particularly to a non-volatile ferroelectric capacitor memory and a method for sensing ferroelectric capacitor data in a memory cell.
BACKGROUND OF THE INVENTION
It is well known that ferroelectric material performs a hysteresis characteristic and is capable of retaining polarization state even when the applied power is removed from the material. The ferroelectric capacitor memory cell can memorize “1” or “0” using different polarization state. The field voltage can be applied across the capacitor to read the memorized data, “1” or “0”, because different polarization state represents different capacitance which can be sensed by sensor device.
FIG. 1
illustrates a hysteresis curve of ferroelectrical material, wherein the abscissa represents the field voltage applied to the material and the ordinate represents the polarization of the material. If a capacitor is formed using a ferroelectric material between its plates, because of the hysteresis curve, the flow of current through the capacitor will depend on the prior history of the voltages applied to the device. If a ferroelectric capacitor is in a initial state on which zero volt is applied, point A or point D may indicate polarization. Assuming that point A in
FIG. 1
indicates polarization, a positive voltage which is greater than the coercive voltage (referring to point B in
FIG. 1
) is applied across the capacitor, then the capacitor will conduct current and have a new polarization (referring to point C in
FIG. 1
) state. When the applied voltage is removed, the ferroelectric capacitor will maintain the same polarization state as shown at point D instead of returning to the state as shown at point A. A positive voltage continuously applying across the capacitor will cause a little change on the polarization. However, an enough negative voltage will cause the polarization to vary from point D to point E as indicated in FIG.
1
. Once the negative voltage is removed from the capacitor, the ferroelectric capacitor will maintain the same polarization state and the curve moves to point A. Therefore, point A and point D respectively represent two different logical states when zero volt is applied across the capacitor.
Nonvolatile semiconductor ferroelectric memories can memorize “1” or “0” using different polarization state, and such polarization state will not be destroyed when the power is removed from the memory. Referring
FIG. 2
, is a schematic diagram of a 2T/2C memory cell
200
(two-transistors, two-capacitors). Ferroelectric memory circuits includes a word line
201
,two bit lines
202
and
203
coupling to a sense amplifier
209
, a plate line
208
for driving ferroelectric capacitor and a memory cell
200
including transistors
204
,
205
and ferroelectric capacitors
206
,
207
.
The conventional detecting scheme can be divided into two types: plate line driven and bit line driven. For example, a timing diagram for the plate line driven of a 2T/2C memory cell such as cell
200
is shown in FIG.
3
. Assuming that the polarization state of ferroelectric capacitor
207
is at point D in FIG.
1
and the polarization state of ferroelectric capacitor
206
is at point A in FIG.
1
. At time T
1
, the word line
201
is stepped from the initial logical zero voltage to a logical one voltage to drive transistor
204
and
205
. At time T
2
, the plate line
208
is pulsed to a logical one voltage. The polarization state stored in the ferroelectric capacitor
206
will be changed, from point A to point DC, a large amount of electrical charge being transferred from the ferroelectric capacitor
206
to the bit line
202
. The polarization state stored in the ferroelectric capacitor
207
changes from point D to point C maintains the same polarization state, only small amount of electrical charge would be transferred from the ferroelectric capacitor
207
to the bit line
203
. At time T
3
the sensing amplifier
209
is enabled and the differential charge on the bit lines
202
and
203
can be sensed and converted into a valid logical state. At time T
4
and T
5
, the original data is written into the memory cell
200
to restore the data.
On the other hand, a timing diagram for the bit line driven of is shown in FIG.
4
. Assuming that the polarization state of ferroelectric capacitor
207
is at point D in FIG.
1
and the polarization state of ferroelectric capacitor
206
is at point A in FIG.
1
. At time T
1
, the bit line
202
and
203
are precharged to a logical one voltage, usually five volts. At time T
2
, the word line
201
is stepped from the initial logical zero voltage to a logical one voltage to drive transistor
204
and
205
. The polarization state stored in the ferroelectric capacitor
206
will be changed from point A to point CD and the polarization state in the ferroelectric capacitor
207
will be changed from point D to point C maintains the same polarization state due to the plate line
208
in the logical zero voltage. The electrical charge being transferred from the bit line
202
and
203
to the ferroelectric capacitors
206
and
207
. The bit lines will exhibit different voltage due to the switched ferroelectric capacitor. At time T
3
the sensing amplifier
209
is enabled and the differential charge on the bit lines
202
and
203
can be sensed and converted into a valid logical state. At time T
4
, the plate line
208
is pulsed to logical one voltage to restore the original data. And at time T
5
, the bit lines are discharged to process the next reading cycle.
The conventional detecting scheme described in above has the following problems to be resolved. The main shortcoming of the plate line driven is slow speed due to large capacitance of ferroelectric capacitor that the plate line need to drive. The two ferroelectric capacitors
206
and
207
are connected to plate line
208
, and at time T
2
, the plate line
208
is pulsed to logical one voltage to read the data stored in memory cell
200
. However, since the plate line must transition the polarization state of ferroelectric capacitor, T
2
has the issues of the heavier loading for plate line, that will be the bottleneck of fast access and cycle time. And bit line driven scheme is to overcome the shortcoming, the bit line driven method do not need drive the plate line in reading cycle but the plate line also is needed to drive for write back action at time T
4
to transit the connected ferroelectric capacitor polarization state. Although it gets fast access time, it has no much improvement on cycle time.
SUMMARY OF THE INVENTION
The conventional detecting scheme, plate line driven or bit line driven, for operation cycle of a 2T/2C (two-transistors, two-capacitors) and 1T/1C (one-transistor, one-capacitor) often involves a destructive read for the ferroelectric capacitor changes state from one polarization state to the other. In order to maintain the original data (original polarization state), a restore cycle is needed for restoring the original data. The time required for restoring data may reduce the operation speed.
From the foregoing, in accordance with the main purpose of this present invention, the disclosed detecting scheme may increase the operation speed.
A 2T/2C memory cell includes a first transistor coupled to a first ferroelectric capacitor, and a second transistor coupled to a second ferroelectric capacitor. Ferroelectric capacitors store complementary polarization states, which defines a single data state of memory cell. The plate line is coupled to one side of the first and second ferroelectric capacitors. The word line is coupled to the gates of the first and second transistors. The first bit line and second bit line are couples to the source/drain of the first transistor and second transistor. According to the present invention, the disclosed detecting scheme precharges the first and second bit lines to logical one voltage, setting the word line and plate line to logical zero voltage, stepping the word line from the in

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