Non-volatile memory cell and method of forming the same

Details Non-volatile memory cell and method of forming the same Non-volatile memory cell and method of forming the same

2006-10-03

2006-10-03

Parker, Kenneth (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S532000, C257SE27048, C257SE27071, C257SE27093

Reexamination Certificate

active

07115938

ABSTRACT:
A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common ploysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common ploysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common ploysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

REFERENCES:
patent: 4173819 (1979-11-01), Kinoshita
patent: 4295264 (1981-10-01), Rogers
patent: 4419682 (1983-12-01), Masuoka
patent: 5962887 (1999-10-01), Manning et al.
patent: 6191980 (2001-02-01), Kelley et al.
patent: 2004/0217444 (2004-11-01), Ooms et al.

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