Non-volatile memory cell

Details Non-volatile memory cell Non-volatile memory cell

2000-09-11

2002-11-26

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S316000

Reexamination Certificate

active

06486509

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a fast-programmable Flash EEPROM (Electrically Erasable Programmable Read-Only Memory) device relying on the Source-Side Injection (SSI) mechanism for programming and that is particularly suited for high density low-voltage low-power applications.
BACKGROUND OF THE PRESENT INVENTION
Nowadays, most Flash memory cells integrated in or on an integrated circuit or chip use Channel Hot Electron Injection (CHEI) at the drain side of the memory cell, or Fowler-Nordheim Tunneling (FNT) for programming. The CHEI mechanism provides a relatively high programming speed (~10 &mgr;s) at the expense of a high power consumption (~1 mA/bit) which limits the number of transistor cells that can be programmed simultaneously (so-called page-mode programming) to a maximum of 8 bytes (Y. Miyawaki et al., IEEE J. Solid-State Circuits, vol.27, p.583, 1992). In order to allow a scaling of the transistor cell dimensions towards 0.35 &mgr;m and below, supply voltage scaling from 5V towards 3.3V and below becomes mandatory. This supply voltage scaling is known to degrade the CHEI efficiency, and hence the corresponding programming speed, considerably. This is because the high power needed to trigger the CHEI can not be easily supplied on-chip from a high voltage generator or charge pumping circuit.
On the other hand, FNT provides slower programming times (~100 &mgr;s) and a low power consumption which allows larger pages (~4 kbit) in order to reduce the effective programming time to 1 &mgr;s/byte (T. Tanaka et al., IEEE J. Solid-State Circuits, vol.29, p.1366, 1994). Improvements to this class of memory cells, however, are limited by tunnel-oxide scaling limits and by the very high voltages (~18V) needed on chip for FNT, both compromising reliability of the transistor memory cell and process scalability.
The recent success of SSI as a viable alternative over FNT and CHEI for Flash programming, is mainly due to its unique combination of moderate-to-low power consumption with very high programming speed at moderate voltages. A typical example of such a device relying on SSI for programming is the Applicant's High Injection Metal-Oxide-Semiconductor or HIMOS™ memory cell (J. Van Houdt et al., U.S. Pat. Nos. 5,583,810 and 5,583,811, and EP-A-0501941). A speed-optimised implementation of the HIMOS™ cell in a 0.7-&mgr;m CMOS technology exhibits a 400 nanoseconds programming time while consuming only a moderate current (~35 &mgr;A/cell) from a 5V supply. This result is obtained when biasing the device at the maximum gate current, i.e. at a control-gate voltage (Vcg) of 1.5 V. The corresponding cell area is in the order of 15 &mgr;m
2
for a 0.7-&mgr;m embedded Flash memory technology when implemented in a contactless virtual ground array as described in co-pending application EP-A-0762429. In terms of the feature size F (i.e. the smallest dimension on chip for a given technology), this corresponds to ~30F
2
for a 0.7-&mgr;m technology. This is fairly large as compared to the high density Flash memory concepts which are all in the ~10 F
2
range.
Due to the growing demand for higher memory density applications, also in embedded memory applications like e.g. smart-cards and embedded microcontrollers, a continuous increase in array density and the scaling of the supply voltage become mandatory. This evolution calls for more aggressive cell-area scaling and for low-voltage and low-power operation. In the co-pending application EP-A0762429, a novel programming scheme is described which reduces the power consumption during the write operation considerably. Also, the used write voltages are expected to scale with the supply voltage V
supply
since the SSI mechanism only requires the floating-gate channel to stay in the linear regime for fast programming (see e.g. J. Van Houdt et al., IEEE Trans. Electron Devices, vol.ED-40, p.2255, 1993). Therefore, the necessary Program-Gate voltage V
pg
for fast programming is given by:
V
pg
≈(
V
supply
+V
th
)/
p
  (1)
where V
th
is the intrinsic threshold voltage of the floating gate transistor (~0.5V) and p is the coupling ratio from program gate to floating gate (typically ~50%). According to Eq. (1), V
pg
is thus expected to scale twice as fast as the supply voltage in a first order calculation. It can be concluded that the high programming voltage is scaling very well with the supply voltage which offers enough margin in order for the high voltage circuitry to follow the minimum design rule. There is, however, the drawback of the additional program gate in the HIMOS concept which increases the cell area considerably in the case of a double polysilicon technology. Furthermore, since both control gate and program gate are formed in the same (second) polysilicon layer, the process requires special polysilicon etching recipes in order to remove the polysilicon stringers between control gate and program gate.
AIMS OF THE PRESENT INVENTION
It is an aim of the present invention to suggest a flash memory cell structure that reconciles the possibility for having a small cell size with a high degree of CMOS compatibility.
Thus, the present invention aims to reach a very compact, though still CMOS-compatible, cell geometry that paves the way to higher density low-voltage applications.
More particularly, the present invention aims to suggest a cell allowing for a high integration density without considerably affecting the basic CMOS process, therefore rendering it into a highly competitive memory technology with a low development entry cost, especially in the deep-submicron range.
BRIEF SUMMARY OF THE INVENTION
A first object of the present invention is a non-volatile memory cell comprising a semiconductor substrate including a source region and a drain region with a channel region therebetween; a floating gate of a conductive material at least partially extending over a first portion of said channel region; a control gate of a conductive material at least partially extending over a second portion of the channel region; an additional program gate of a conductive material at least partially overlapping said floating gate and preferably said control gate being capacitively coupled through a dielectric layer to said floating gate.
According to a first preferred embodiment, the control gate is partially overlapping through a (thin) polyoxide layer the floating gate.
According to a second preferred embodiment, the floating gate is partially overlapping through a (thin) polyoxide layer the control gate.
A second object of the present invention is to suggest a method of fabricating a non-volatile memory cell, preferably as described hereabove, wherein on a substrate including a source region and a drain region with a channel region therebetween, at least:
a first polysilicon layer is deposited and selectively removed in order to form at least a part of either a floating gate or a control gate at least partially extending over a portion of said channel region,
a second polysilicon layer is deposited and selectively removed in order to form either a control gate or a floating gate extending over the complementary portion of the channel region and partially overlapping said first polysilicon layer,
a third polysilicon layer is deposited and selectively removed in order to form a program gate at least partially overlapping at least one of the two first polysilicon layers.
According to a preferred embodiment, a first interpoly dielectric layer is formed between the first and second polysilicon layers.
According to another preferred embodiment, a high quality dielectric is formed on the top of the two first polysilicon layers before depositing the third polysilicon layer.
A third object of the present invention is to suggest a contacted array configuration of non-volatile memory cells as described hereabove.
A fourth object of the present invention is to suggest a contactless array configuration of non-volatile memory cells as described hereabove.
The term “supply voltage” as used throughout the specification is well un

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