Non-volatile memory architecture employing bipolar...

Details Non-volatile memory architecture employing bipolar... Non-volatile memory architecture employing bipolar...

2008-01-29

2008-01-29

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Resistive

C365S100000, C365S177000

Reexamination Certificate

active

07324366

ABSTRACT:
A nonvolatile memory array includes a plurality of word lines, a plurality of bit lines, a plurality of source lines, and a plurality of nonvolatile memory cells. Each of at least a subset of the plurality of memory cells has a first terminal connected to one of the plurality of word lines, a second terminal connected to one of the plurality of bit lines, and a third terminal connected to one of the plurality of source lines. At least one of the memory cells includes a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to one of a corresponding first one of the bit lines and a corresponding first one of the source lines, and a metal-oxide-semiconductor device including first and second source/drains and a gate. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a corresponding second one of the bit lines, and the gate is adapted for connection to a corresponding one of the word lines. For at least a subset of the plurality of memory cells, each pair of adjacent memory cells along a given word line shares either the same bit line or the same source line.

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patent: 2006/0110878 (2006-05-01), Lung et al.

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