Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2005-08-18
2009-06-23
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S257000, C257SE21179
Reexamination Certificate
active
07550334
ABSTRACT:
A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate (101) having an insulating surface, active layer side ends (110) are tapered. This makes the thickness of a first insulating film (106), which is formed by a thermal oxidization process, at the active layer side ends (110) the same as the thickness of the rest of the first insulating film. Therefore local thinning of the first insulating film does not take place. Moreover, the tapered active layer side ends hardly tolerate electric field concentration at active layer side end corners (111). Accordingly, a leak current from an electric charge accumulating layer (107) to the active layer (105) is reduced to improve the electric charge holding characteristic. As a result, the first insulating film can be further made thin to obtain a high performance non-volatile memory that operates at a low voltage and consumes less power.
REFERENCES:
patent: 3890632 (1975-06-01), Ham et al.
patent: 4334347 (1982-06-01), Goldsmith et al.
patent: 5470762 (1995-11-01), Codama et al.
patent: 5478766 (1995-12-01), Park et al.
patent: 5643826 (1997-07-01), Ohtani et al.
patent: 5728259 (1998-03-01), Suzawa et al.
patent: 5757030 (1998-05-01), Codama et al.
patent: 5840600 (1998-11-01), Yamazaki et al.
patent: 5888858 (1999-03-01), Yamazaki et al.
patent: 5923962 (1999-07-01), Ohtani et al.
patent: 6097051 (2000-08-01), Torii et al.
patent: 6124153 (2000-09-01), Lee et al.
patent: 6180439 (2001-01-01), Yamazaki et al.
patent: 6335716 (2002-01-01), Yamazaki et al.
patent: 6509217 (2003-01-01), Reddy
patent: 6787403 (2004-09-01), Inoue et al.
patent: 6808963 (2004-10-01), Ishida et al.
patent: 2002/0171085 (2002-11-01), Suzawa et al.
patent: 07-130652 (1995-05-01), None
patent: 08-181231 (1996-07-01), None
patent: 11-143379 (1999-05-01), None
S. Isomae et al., “Cross Sectional TEM Observation of VLSI Devices and Thermal Oxide Morphology”, Extended Abstracts of the 18th (1986 International) Conference on Solid State Devices and Materials, Aug. 20-22, 1986, pp. 517-520.
R.B. Marcus et al., “The Oxidation of Shaped Silicon Surfaces”, Journal of the Electrochemical Society, vol. 129, No. 6, Jun. 1982, pp. 1278-1282.
Kato Kiyoshi
Kurokawa Yoshiyuki
Booth Richard A.
Costellia Jeffrey L.
Nixon & Peabody LLP
Semiconductor Energy Laboratory Co,. Ltd.
LandOfFree
Non-volatile memory and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile memory and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile memory and method of manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4063950