Non-volatile memory and method for fabricating same

Details Non-volatile memory and method for fabricating same Non-volatile memory and method for fabricating same

1991-08-14

1993-08-03

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257323, 257390, 257401, H01L 2968, H01L 2710

Patent

active

052332101

ABSTRACT:
A non-volatile memory includes a sheet-shaped source line consisting of a conductive layer. The source line includes an opening at an area including a bit contact area above a drain diffusion layer. The bit contact is formed through self-alignment to the opening of the source line and a control gate electrode. In such a structure, a pitch of the bit contact in the direction parallel to the control gate electrode can be set to be a value twice of the minimum size in design.

REFERENCES:
patent: 5053841 (1991-10-01), Miyakawa et al.
Katznelson et al., "An Erase Model for FAMOS EPROM Devices," IEEE Transactions and Electrical Devices, vol. ED-17, No. 9, Sep. 1980, pp. 1744-1751.
Hisamune et al., "A 3.6 .mu.m.sup.2 Memory Cell Structure for 16 Mb EPROMS," IEDM 89, pp. 583-586.

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