Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-07-08
2004-09-21
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C438S287000
Reexamination Certificate
active
06794701
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a structure of a semiconductor device and the fabrication thereof. More particularly, the present invention relates to a structure of a non-volatile memory (NVM) and the fabrication thereof.
2. Description of Related Art
Plasma techniques are frequently used in a manufacturing process of a non-volatile memory having a charge trapping layer for data storage. However, when a transient charge unbalance occurs in the plasma, some charges will move along the metal portions on the wafer. Such an effect is called the antenna effect. Consequently, some charges are injected into the charge trapping layers of the non-volatile memory to unevenly raise the threshold voltages (V
T
) of the memory cells, i.e., to produce a programming effect. Therefore, the V
T
distribution of the non-volatile memory is much broadened, being usually from 0.3V to 0.9V.
In order to prevent the programming effect caused by the antenna effect, a diode is formed in the substrate to electrically connect with the word-line in the prior art. When the charges accumulated on the word-line reach a certain amount to produce a voltage higher than the breakdown voltage of the diode, the charges are released in a breakdown manner. However, the programming effect cannot be completely eliminated by this method since there may still be some charges injected into the charge trapping layer even if the voltage produced by the charges accumulated on the word-line is lower than the breakdown voltage of the diode. Moreover, by using this method, the input voltage of the non-volatile memory will be lowered by the diode to adversely decrease the operating speed of the memory device.
SUMMARY OF THE INVENTION
Accordingly, this invention provides a non-volatile memory and the fabrication thereof to prevent the charge trapping layer of a non-volatile memory from being damaged in a plasma process.
This invention also provides a non-volatile memory and the fabrication thereof to prevent the non-volatile memory from being programmed in a plasma process, so that the threshold voltages (V
T
) of the memory cells are not raised and the V
T
distribution is not broadened.
This invention also provides a non-volatile memory and the fabrication thereof to avoid the input voltage of the memory device from being lowered, so that the operating speed of the memory device is not decreased.
The non-volatile memory of this invention comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over the substrate. In addition, there is a protective metal line electrically connecting with the word-line and with a grounding doped region in the substrate via two contacts, respectively. The protective metal line has a resistance higher than that of the word-line.
In the method of fabricating a non-volatile memory of this invention, a non-volatile cell is formed on a substrate and then a grounding doped region is formed in the substrate. Two contacts are then formed over the substrate to electrically connect with the word-line and the grounding doped region, respectively. A protective metal line is formed over the substrate to electrically connect with the grounding doped region and with the word-line via the two contacts, respectively. The protective metal line has a resistance higher than that of the word-line so that the protective metal line can be blown by applying a large current when the manufacturing process is completed.
Because this invention uses a protective metal line with a high resistance to conduct the charges produced in a plasma process into the substrate, the charge trapping layer of the non-volatile memory is not damaged and the memory cells are not programmed at random. Moreover, since the protective metal line has a high resistance, it can be easily blown by applying a large current to disconnect the word-line from the grounding doped region when the manufacturing process is completed. Consequently, the input voltage of the memory device is not lowered and the operating speed of the memory device is not decreased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5543344 (1996-08-01), Hsu et al.
patent: 6277691 (2001-08-01), Quoc et al.
patent: 6337502 (2002-01-01), Eitan et al.
patent: 6469342 (2002-10-01), Kuo et al.
patent: 6620694 (2003-09-01), Kuo et al.
Huang Shou-Wei
Kuo Tung-Cheng
Liu Chien-Hung
Pan Shyi-Shuh
J. C. Patents
Le Thao P.
Macronix International Co. Ltd.
Nelms David
LandOfFree
Non-volatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3212516